From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 18 Sep 2019 15:45:07 +0000 (+0200)
Subject: better handling of lut and begin/end add
X-Git-Tag: working-ls180~1059^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8badd4d812e30c79a3fe75694ef8d8289f08abc7;p=yosys.git

better handling of lut and begin/end add
---

diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index a41ff1a35..2fc2034a6 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -5,8 +5,12 @@ module EFX_LUT4(
    input I2,
    input I3
 );
-   parameter LUTMASK  = 16'h0000;
-	assign O = LUTMASK >> {I3, I2, I1, I0};   
+	parameter LUTMASK = 16'h0000;
+
+	wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
+	wire [3:0] s2 = I2 ?      s3[ 7:4] :      s3[3:0];
+	wire [1:0] s1 = I1 ?      s2[ 3:2] :      s2[1:0];
+	assign O = I0 ? s1[1] : s1[0];	   
 endmodule
 
 module EFX_ADD(
@@ -71,10 +75,12 @@ module EFX_FF(
          begin
             always @(posedge clk)
                if (ce)
+               begin
                   if (sr)
                      Q <= SR_VALUE;
                   else
-                     Q <= d;            
+                     Q <= d;
+               end
          end
       end
       else
@@ -164,4 +170,4 @@ module EFX_RAM_5K(
 			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
 			    (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
    
-endmodule
+endmodule
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