From: Hongtao Liu Date: Sat, 26 Oct 2019 02:40:19 +0000 (+0000) Subject: Adjust predicates and constraints of scalar insns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bbf3dea78325c39d7750e815024eef960415592;p=gcc.git Adjust predicates and constraints of scalar insns. Changelog gcc/ * config/i386/sse.md (_vm3, _vm3, _vmsqrt2, _vm3, _vmmaskcmp3): Change predicates from vector_operand to nonimmediate_operand, constraints xBm to xm, since scalar operations don't need memory address alignment. (avx512f_vmcmp3, avx512f_vmcmp3_mask): Replace round_saeonly_nimm_predicate with round_saeonly_nimm_scalar_predicate. (fmai_vmfmadd_, fmai_vmfmsub_, fmai_vmfnmadd_,fmai_vmfnmsub_, *fmai_fmadd_, *fmai_fmsub_, *fmai_fnmadd_, *fmai_fnmsub_, avx512f_vmfmadd__mask3, avx512f_vmfmadd__maskz_1, *avx512f_vmfmsub__mask, avx512f_vmfmsub__mask3, *avx512f_vmfmsub__maskz_1, *avx512f_vmfnmadd__mask, *avx512f_vmfnmadd__mask3, *avx512f_vmfnmadd__maskz_1, *avx512f_vmfnmsub__mask, *avx512f_vmfnmsub__mask3, *avx512f_vmfnmsub__maskz_1, cvtusi232, cvtusi264, ): Replace round_nimm_predicate with round_nimm_scalr_predicate. (avx512f_sfixupimm, avx512f_sfixupimm_mask, avx512er_vmrcp28, avx512er_vmrsqrt28, ): Replace round_saeonly_nimm_predicate with round_saeonly_nimm_scalar_predicate. (avx512dq_vmfpclass): Replace vector_operand with nonimmediate_operand. * config/i386/subst.md (round_scalar_nimm_predicate, round_saeonly_scalar_nimm_predicate): Replace vector_operand with nonimmediate_operand. From-SVN: r277470 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7015e1b8584..3dc1b7c08a3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,48 @@ +2019-10-26 Hongtao Liu + + * config/i386/sse.md + (_vm3, + _vm3, + _vmsqrt2, + _vm3, + _vmmaskcmp3): + Change predicates from vector_operand to nonimmediate_operand, + constraints xBm to xm, since scalar operations don't need + memory address alignment. + (avx512f_vmcmp3, + avx512f_vmcmp3_mask): Replace + round_saeonly_nimm_predicate with + round_saeonly_nimm_scalar_predicate. + (fmai_vmfmadd_, fmai_vmfmsub_, + fmai_vmfnmadd_,fmai_vmfnmsub_, + *fmai_fmadd_, *fmai_fmsub_, + *fmai_fnmadd_, *fmai_fnmsub_, + avx512f_vmfmadd__mask3, + avx512f_vmfmadd__maskz_1, + *avx512f_vmfmsub__mask, + avx512f_vmfmsub__mask3, + *avx512f_vmfmsub__maskz_1, + *avx512f_vmfnmadd__mask, + *avx512f_vmfnmadd__mask3, + *avx512f_vmfnmadd__maskz_1, + *avx512f_vmfnmsub__mask, + *avx512f_vmfnmsub__mask3, + *avx512f_vmfnmsub__maskz_1, + cvtusi232, + cvtusi264, ): Replace + round_nimm_predicate with round_nimm_scalr_predicate. + (avx512f_sfixupimm, + avx512f_sfixupimm_mask, + avx512er_vmrcp28, + avx512er_vmrsqrt28, + ): Replace round_saeonly_nimm_predicate with + round_saeonly_nimm_scalar_predicate. + (avx512dq_vmfpclass): Replace + vector_operand with nonimmediate_operand. + * config/i386/subst.md (round_scalar_nimm_predicate, + round_saeonly_scalar_nimm_predicate): Replace + vector_operand with nonimmediate_operand. + 2019-10-26 Hongtao Liu PR target/89071 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index ce0dccf3e08..077c1d6da1d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1863,7 +1863,7 @@ (vec_merge:VF_128 (plusminus:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "vector_operand" "xBm,")) + (match_operand:VF_128 2 "nonimmediate_operand" "xm,")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -1940,7 +1940,7 @@ (vec_merge:VF_128 (multdiv:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "vector_operand" "xBm,")) + (match_operand:VF_128 2 "nonimmediate_operand" "xm,")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -2135,7 +2135,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=x,v") (vec_merge:VF_128 (sqrt:VF_128 - (match_operand:VF_128 1 "vector_operand" "xBm,")) + (match_operand:VF_128 1 "nonimmediate_operand" "xm,")) (match_operand:VF_128 2 "register_operand" "0,v") (const_int 1)))] "TARGET_SSE" @@ -2368,7 +2368,7 @@ (vec_merge:VF_128 (smaxmin:VF_128 (match_operand:VF_128 1 "register_operand" "0,v") - (match_operand:VF_128 2 "vector_operand" "xBm,")) + (match_operand:VF_128 2 "nonimmediate_operand" "xm,")) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -3012,7 +3012,7 @@ (vec_merge:VF_128 (match_operator:VF_128 3 "sse_comparison_operator" [(match_operand:VF_128 1 "register_operand" "0,x") - (match_operand:VF_128 2 "vector_operand" "xBm,xm")]) + (match_operand:VF_128 2 "nonimmediate_operand" "xm,xm")]) (match_dup 1) (const_int 1)))] "TARGET_SSE" @@ -3097,7 +3097,7 @@ (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "" "") + (match_operand:VF_128 2 "" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (const_int 1)))] @@ -3113,7 +3113,7 @@ (and: (unspec: [(match_operand:VF_128 1 "register_operand" "v") - (match_operand:VF_128 2 "" "") + (match_operand:VF_128 2 "" "") (match_operand:SI 3 "const_0_to_31_operand" "n")] UNSPEC_PCMP) (and: @@ -4742,8 +4742,8 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand") - (match_operand:VF_128 2 "") - (match_operand:VF_128 3 "")) + (match_operand:VF_128 2 "") + (match_operand:VF_128 3 "")) (match_dup 1) (const_int 1)))] "TARGET_FMA") @@ -4753,9 +4753,9 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand") - (match_operand:VF_128 2 "") + (match_operand:VF_128 2 "") (neg:VF_128 - (match_operand:VF_128 3 ""))) + (match_operand:VF_128 3 ""))) (match_dup 1) (const_int 1)))] "TARGET_FMA") @@ -4765,9 +4765,9 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "")) + (match_operand:VF_128 2 "")) (match_operand:VF_128 1 "register_operand") - (match_operand:VF_128 3 "")) + (match_operand:VF_128 3 "")) (match_dup 1) (const_int 1)))] "TARGET_FMA") @@ -4777,10 +4777,10 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "")) + (match_operand:VF_128 2 "")) (match_operand:VF_128 1 "register_operand") (neg:VF_128 - (match_operand:VF_128 3 ""))) + (match_operand:VF_128 3 ""))) (match_dup 1) (const_int 1)))] "TARGET_FMA") @@ -4790,8 +4790,8 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ", v") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 2 "" ", v") + (match_operand:VF_128 3 "" "v,")) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" @@ -4806,9 +4806,9 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ",v") + (match_operand:VF_128 2 "" ",v") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" @@ -4823,9 +4823,9 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 3 "" "v,")) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" @@ -4840,10 +4840,10 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_dup 1) (const_int 1)))] "TARGET_FMA || TARGET_AVX512F" @@ -4859,8 +4859,8 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ",v") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 2 "" ",v") + (match_operand:VF_128 3 "" "v,")) (match_dup 1) (match_operand:QI 4 "register_operand" "Yk,Yk")) (match_dup 1) @@ -4877,8 +4877,8 @@ (vec_merge:VF_128 (vec_merge:VF_128 (fma:VF_128 - (match_operand:VF_128 1 "" "%v") - (match_operand:VF_128 2 "" "") + (match_operand:VF_128 1 "" "%v") + (match_operand:VF_128 2 "" "") (match_operand:VF_128 3 "register_operand" "0")) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) @@ -4909,8 +4909,8 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ",v") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 2 "" ",v") + (match_operand:VF_128 3 "" "v,")) (match_operand:VF_128 4 "const0_operand" "C,C") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) @@ -4928,9 +4928,9 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ",v") + (match_operand:VF_128 2 "" ",v") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_dup 1) (match_operand:QI 4 "register_operand" "Yk,Yk")) (match_dup 1) @@ -4947,8 +4947,8 @@ (vec_merge:VF_128 (vec_merge:VF_128 (fma:VF_128 - (match_operand:VF_128 1 "" "%v") - (match_operand:VF_128 2 "" "") + (match_operand:VF_128 1 "" "%v") + (match_operand:VF_128 2 "" "") (neg:VF_128 (match_operand:VF_128 3 "register_operand" "0"))) (match_dup 3) @@ -4966,9 +4966,9 @@ (vec_merge:VF_128 (fma:VF_128 (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 2 "" ",v") + (match_operand:VF_128 2 "" ",v") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_operand:VF_128 4 "const0_operand" "C,C") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) @@ -4986,9 +4986,9 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 3 "" "v,")) (match_dup 1) (match_operand:QI 4 "register_operand" "Yk,Yk")) (match_dup 1) @@ -5006,8 +5006,8 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" "")) - (match_operand:VF_128 1 "" "%v") + (match_operand:VF_128 2 "" "")) + (match_operand:VF_128 1 "" "%v") (match_operand:VF_128 3 "register_operand" "0")) (match_dup 3) (match_operand:QI 4 "register_operand" "Yk")) @@ -5024,9 +5024,9 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") - (match_operand:VF_128 3 "" "v,")) + (match_operand:VF_128 3 "" "v,")) (match_operand:VF_128 4 "const0_operand" "C,C") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) @@ -5044,10 +5044,10 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_dup 1) (match_operand:QI 4 "register_operand" "Yk,Yk")) (match_dup 1) @@ -5065,8 +5065,8 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" "")) - (match_operand:VF_128 1 "" "%v") + (match_operand:VF_128 2 "" "")) + (match_operand:VF_128 1 "" "%v") (neg:VF_128 (match_operand:VF_128 3 "register_operand" "0"))) (match_dup 3) @@ -5084,10 +5084,10 @@ (vec_merge:VF_128 (fma:VF_128 (neg:VF_128 - (match_operand:VF_128 2 "" ",v")) + (match_operand:VF_128 2 "" ",v")) (match_operand:VF_128 1 "register_operand" "0,0") (neg:VF_128 - (match_operand:VF_128 3 "" "v,"))) + (match_operand:VF_128 3 "" "v,"))) (match_operand:VF_128 4 "const0_operand" "C,C") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) @@ -5355,7 +5355,7 @@ (vec_merge:VF_128 (vec_duplicate:VF_128 (unsigned_float: - (match_operand:SI 2 "" ""))) + (match_operand:SI 2 "" ""))) (match_operand:VF_128 1 "register_operand" "v") (const_int 1)))] "TARGET_AVX512F && " @@ -5369,7 +5369,7 @@ (vec_merge:VF_128 (vec_duplicate:VF_128 (unsigned_float: - (match_operand:DI 2 "" ""))) + (match_operand:DI 2 "" ""))) (match_operand:VF_128 1 "register_operand" "v") (const_int 1)))] "TARGET_AVX512F && TARGET_64BIT" @@ -9708,7 +9708,7 @@ (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "" "") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) @@ -9725,7 +9725,7 @@ (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "0") (match_operand:VF_128 2 "register_operand" "v") - (match_operand: 3 "" "") + (match_operand: 3 "" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) @@ -18642,7 +18642,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 - [(match_operand:VF_128 1 "" "")] + [(match_operand:VF_128 1 "" "")] UNSPEC_RCP28) (match_operand:VF_128 2 "register_operand" "v") (const_int 1)))] @@ -18668,7 +18668,7 @@ [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128 - [(match_operand:VF_128 1 "" "")] + [(match_operand:VF_128 1 "" "")] UNSPEC_RSQRT28) (match_operand:VF_128 2 "register_operand" "v") (const_int 1)))] @@ -21888,7 +21888,7 @@ [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: - [(match_operand:VF_128 1 "vector_operand" "vm") + [(match_operand:VF_128 1 "nonimmediate_operand" "vm") (match_operand:QI 2 "const_0_to_255_operand" "n")] UNSPEC_FPCLASS) (const_int 1)))] diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index dd5890584f4..0d376063f48 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -271,7 +271,7 @@ (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "") (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v") (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex") -(define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "vector_operand" "register_operand") +(define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand") (define_subst "round_scalar" [(set (match_operand:SUBST_V 0) @@ -296,7 +296,7 @@ (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "") (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v") (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex") -(define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "vector_operand" "register_operand") +(define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand") (define_subst "round_saeonly_scalar" [(set (match_operand:SUBST_V 0)