From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 20 Sep 2022 20:50:43 +0000 (+0300)
Subject: power_fields: restore class-oriented traversal
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bd5556e723ed2761cc3a3f75af58e0e91e5c44a;p=openpower-isa.git

power_fields: restore class-oriented traversal
---

diff --git a/src/openpower/decoder/power_fields.py b/src/openpower/decoder/power_fields.py
index f39ff386..07dfe70b 100644
--- a/src/openpower/decoder/power_fields.py
+++ b/src/openpower/decoder/power_fields.py
@@ -185,9 +185,9 @@ class Field(Reference, metaclass=FieldMeta):
 
         return _selectconcat(*(self[bit] for bit in tuple(key)))
 
-    def traverse(self, path):
-        span = self.__class__.__members__
-        yield (path, self.storage[span], span)
+    @classmethod
+    def traverse(cls, path):
+        yield (path, cls.__members__)
 
 
 class MappingMeta(type):
@@ -274,8 +274,9 @@ class Mapping(Reference, metaclass=MappingMeta):
 
         return self.__members[key]
 
-    def traverse(self, path=""):
-        for (name, member) in self.__members.items():
+    @classmethod
+    def traverse(cls, path):
+        for (name, member) in cls.__members__.items():
             if name == "_":
                 yield from member.traverse(path=path)
             elif path == "":
diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 75879f86..c1fb4a2f 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1295,10 +1295,11 @@ class BaseRM(_Mapping):
     def disassemble(self, verbosity=Verbosity.NORMAL):
         if verbosity >= Verbosity.VERBOSE:
             indent = (" " * 4)
-            for (name, value, members) in self.traverse(path="RM"):
+            for (name, span) in self.traverse(path="RM"):
+                value = self.storage[span]
                 yield f"{name}"
                 yield f"{indent}{int(value):0{value.bits}b}"
-                yield f"{indent}{', '.join(map(str, members))}"
+                yield f"{indent}{', '.join(map(str, span))}"
 
 
 class FFPRRc1BaseRM(BaseRM):
diff --git a/src/openpower/sv/sv_binutils.py b/src/openpower/sv/sv_binutils.py
index 6ace71b2..713c272e 100644
--- a/src/openpower/sv/sv_binutils.py
+++ b/src/openpower/sv/sv_binutils.py
@@ -320,7 +320,7 @@ class Instruction(Struct, c_tag="svp64_insn"):
 
         yield from super().c_decl()
         yield ""
-        for (path, field) in _SVP64Instruction.traverse():
+        for (path, field) in _SVP64Instruction.traverse(path="svp64_insn"):
             yield from getter(path, field)
             yield from setter(path, field)
 
diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index eb1f8115..29047b11 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1455,8 +1455,9 @@ class SVP64Asm:
             if not v30b_op.endswith('.'):
                 v30b_op += rc
             yield "%s %s" % (v30b_op, ", ".join(v30b_newfields))
-        for (field, value, span) in svp64_insn.traverse("SVP64"):
-            log(field, f"{value.value:0{value.bits}b}", span)
+        for (name, span) in svp64_insn.traverse("SVP64"):
+            value = svp64_insn.storage[span]
+            log(name, f"{value.value:0{value.bits}b}", span)
         log("new v3.0B fields", v30b_op, v30b_newfields)
 
     def translate(self, lst):