From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 May 2021 14:41:14 +0000 (+0100)
Subject: allow unaligned access exception to be raised in ISACaller mem simulator
X-Git-Tag: 0.0.3~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bde567edd30d4b3ddfb7ba1c885f883284cc417;p=openpower-isa.git

allow unaligned access exception to be raised in ISACaller mem simulator
---

diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py
index c92d70ad..2b6c118d 100644
--- a/src/openpower/decoder/isa/mem.py
+++ b/src/openpower/decoder/isa/mem.py
@@ -27,6 +27,9 @@ def swap_order(x, nbytes):
     return x
 
 
+class MemException(Exception):
+    pass
+
 
 class Mem:
 
@@ -72,7 +75,10 @@ class Mem:
                 swap, check_in_mem, instr_fetch)
         remainder = address & (self.bytes_per_word - 1)
         address = address >> self.word_log2
-        assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
+        if remainder & (width - 1) != 0:
+            exc = MemException("unaligned", "Unaligned access unsupported!")
+            exc.dar = address
+            raise exc
         if address in self.mem:
             val = self.mem[address]
         elif check_in_mem:
@@ -97,7 +103,10 @@ class Mem:
         addr = addr >> self.word_log2
         print("Writing 0x{:x} to ST 0x{:x} "
               "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
-        assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
+        if remainder & (width - 1) != 0:
+            exc = MemException("unaligned", "Unaligned access unsupported!")
+            exc.dar = address
+            raise exc
         if swap:
             v = swap_order(v, width)
         if width != self.bytes_per_word: