From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 4 Nov 2020 15:22:53 +0000 (+0000)
Subject: change to use 3.3v on VERSA X3
X-Git-Tag: convert-csv-opcode-to-binary~1868
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bde99745571a03f94f1edc697d24b29e0aa4616;p=libreriscv.git

change to use 3.3v on VERSA X3
---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 203f81bc4..733c56acc 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -187,7 +187,7 @@ Table of connections:
 |-------------|-------------|----------------|-----------|
 |1 GND        | GND         | 4 (GND)        |   Black   |
 |2 NC         | NC          |  NC            |    NC     |
-|3 +2V5       | 2.5V supply | 2 (MCU VDD)    |   Red     |
+|39 +3.3V     | 3.3V supply | 2 (MCU VDD)    |   Red     |
 |4 IO29       |  B19        |    5 (TDI)     |   Green   |
 |5 IO30       |  B12        |    7 (TMS)     |   Blue    |
 |6 IO31       |  B9         |    9 (TCK)     |   White   |