From: Jeff Goeders <jeff.goeders@gmail.com>
Date: Mon, 19 Oct 2020 22:09:04 +0000 (-0600)
Subject: Move signal declarations to before first use
X-Git-Tag: working-ls180~238^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8be56960a26081ab57542d71fb78be594b9e014f;p=yosys.git

Move signal declarations to before first use

Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 40804c367..4162160bb 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -2335,6 +2335,8 @@ parameter integer PREG = 1;
 
 // The multiplier.
 wire signed [35:0] P_MULT;
+wire signed [17:0] A_MULT;
+wire signed [17:0] B_MULT;
 assign P_MULT = A_MULT * B_MULT;
 
 // The cascade output.
@@ -2373,8 +2375,6 @@ always @(posedge CLK) begin
 end
 
 // The register enables.
-wire signed [17:0] A_MULT;
-wire signed [17:0] B_MULT;
 assign A_MULT = (AREG == 1) ? A_REG : A;
 assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
 assign P = (PREG == 1) ? P_REG : P_MULT;