From: Cesar_Strauss <Cesar_Strauss@web>
Date: Sun, 21 Feb 2021 17:57:00 +0000 (+0000)
Subject: Working on the hardware for loop
X-Git-Tag: convert-csv-opcode-to-binary~139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bfc92154aaeec51b94f3edfd261393da02dccdc;p=libreriscv.git

Working on the hardware for loop
---

diff --git a/Cesar_Strauss.mdwn b/Cesar_Strauss.mdwn
index c88b2e074..492a8f24a 100644
--- a/Cesar_Strauss.mdwn
+++ b/Cesar_Strauss.mdwn
@@ -62,6 +62,10 @@ unit tests.
         <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
         Status: in progress  
 
+13. Implement simple VL for-loop in nMigen for TestIssuer  
+        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
+        Status: in progress  
+
 ## Completed but not yet submitted:
 
 1. FSM-based ALU example needed (compliant with ALU CompUnit)