From: Megan Wachs <megan@sifive.com>
Date: Tue, 13 Jun 2017 18:00:29 +0000 (-0700)
Subject: More Peripheral-to-pins cleanups
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8bfda688581488468611dbc46c750fd0910a6e5a;p=sifive-blocks.git

More Peripheral-to-pins cleanups
---

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index d9c3ff4..fc62c6b 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -22,10 +22,10 @@ trait HasPeripheryI2C extends HasSystemNetworks {
 trait HasPeripheryI2CBundle {
   val i2cs: Vec[I2CPort]
 
-  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
-    val pin = Module(new I2CGPIOPort(syncStages))
-    pin.io.i2c <> i
-    pin
+  def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
+    val pins = Module(new I2CGPIOPort(syncStages))
+    pins.io.i2c <> i
+    pins.io.pins
   }
 }
 
diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 7b59896..d22de54 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -43,10 +43,10 @@ trait HasPeripheryPWM extends HasSystemNetworks {
 trait HasPeripheryPWMBundle {
   val pwms: HeterogeneousBag[PWMPortIO]
 
-  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMGPIOPort] = pwms.map { p =>
-    val pin = Module(new PWMGPIOPort(p.c))
-    pin.io.pwm <> p
-    pin
+  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
+    val pins = Module(new PWMGPIOPort(p.c))
+    pins.io.pwm <> p
+    pins.io.pins
   }
 }
 
diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 4361b1a..83e6664 100644
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -23,10 +23,10 @@ trait HasPeripherySPI extends HasSystemNetworks {
 trait HasPeripherySPIBundle {
   val spis: HeterogeneousBag[SPIPortIO]
 
-  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
-    val pin = Module(new SPIGPIOPort(s.c, syncStages))
-    pin.io.spi <> s
-    pin
+  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = spis.map { s =>
+    val pins = Module(new SPIGPIOPort(s.c, syncStages))
+    pins.io.spi <> s
+    pins.io.pins
   }
 }
 
@@ -54,6 +54,15 @@ trait HasPeripherySPIFlash extends HasSystemNetworks {
 
 trait HasPeripherySPIFlashBundle {
   val qspi: HeterogeneousBag[SPIPortIO]
+
+  // It is important for SPIFlash that the syncStages is agreed upon, because
+  // internally it needs to realign the input data to the output SCK.
+  // Therefore, we rely on the syncStages parameter.
+  def SPIFlashtoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = qspi.map { s =>
+    val pins = Module(new SPIGPIOPort(s.c, syncStages))
+    pins.io.spi <> s
+    pins.io.pins
+  }
 }
 
 trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 58b1c9e..e01eb9f 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -30,9 +30,9 @@ trait HasPeripheryUARTBundle {
   }
 
   def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
-    val pin = Module(new UARTGPIOPort(syncStages))
-    pin.io.uart <> u
-    pin.io.pins
+    val pins = Module(new UARTGPIOPort(syncStages))
+    pins.io.uart <> u
+    pins.io.pins
   }
 }