From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Date: Thu, 7 May 2020 20:09:47 +0000 (-0400)
Subject: pan/mdg: Handle dest up/lower correctly with swizzles
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c012c8f8bb1871486d7f46fd98ff97c857fa64d;p=mesa.git

pan/mdg: Handle dest up/lower correctly with swizzles

During emit time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
---

diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c
index 99134ddcfb9..017c74e33bd 100644
--- a/src/panfrost/midgard/midgard_emit.c
+++ b/src/panfrost/midgard/midgard_emit.c
@@ -223,7 +223,11 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
                         if (upper && ins->mask)
                                 assert(nir_alu_type_get_type_size(ins->src_types[i]) <= 16);
 
-                        for (unsigned c = 0; c < 4; ++c) {
+                        bool dest_up =
+                                GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props) ? false :
+                                (first >= 4);
+
+                        for (unsigned c = (dest_up ? 4 : 0); c < (dest_up ? 8 : 4); ++c) {
                                 unsigned v = ins->swizzle[i][c];
 
                                 bool t_upper = v > 3;
@@ -238,16 +242,21 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
                                 /* Use the non upper part */
                                 v &= 0x3;
 
-                                packed |= v << (2 * c);
+                                packed |= v << (2 * (c % 4));
                         }
 
-                        src[i].rep_high = upper;
 
                         /* Replicate for now.. should really pick a side for
                          * dot products */
 
-                        if (ins->alu.reg_mode == midgard_reg_mode_16)
-                                src[i].rep_low = true;
+                        if (ins->alu.reg_mode == midgard_reg_mode_16) {
+                                src[i].rep_low = !upper;
+                                src[i].rep_high = upper;
+                        } else if (ins->alu.reg_mode == midgard_reg_mode_32) {
+                                src[i].rep_low = upper;
+                        } else {
+                                unreachable("Unhandled reg mode");
+                        }
                 }
 
                 src[i].swizzle = packed;