From: lkcl <lkcl@web>
Date: Sat, 29 Jun 2019 18:38:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4339
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c07a33c7c0b5afb0f60f46e78172c5e164ee98d;p=libreriscv.git

---

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index f20870c12..669bcce9f 100644
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -25,32 +25,25 @@ as follows:
 
 [[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]]
 
-Note: this format is very similar to that used in [[sv_prefix_proposal]]
+Note: The VL Block format is similar to that used in [[sv_prefix_proposal]].
 
-If vlt is 0, VLEN is a 5 bit immediate value, offset by one (i.e
-a bit sequence of 0b00000 represents VL=1 and so on). If vlt is 1,
-it specifies the scalar register from which VL is set by this VBLOCK
-instruction group. VL, whether set from the register or the immediate,
-is then modified (truncated) to be MIN(VL, MAXVL), and the result stored
-in the scalar register specified in VLdest. If VLdest is zero, no store
-in the regfile occurs (however VL is still set).
+* Mode 0b00: set VL to the immediate, truncated to not exceed MVL. Register rd is also set to the same value, if not x0.
+* Mode 0b01: follow [[sv.setvl]] rules except with RVC style registers in the range x8-x15 for rs1 and rd.
+* Mode 0b10: set both MVL and VL to the immediate. Register rd is also set if not x0.
+* Mode 0b11: reserved. All fields must be zero.
 
-This option will typically be used to start vectorised loops, where
+Mode 0b01 will typically be used to start vectorised loops, where
 the VBLOCK instruction effectively embeds an optional "SETSUBVL, SETVL"
 sequence (in compact form).
 
-When bit 15 is set to 1, MAXVL and VL are both set to the immediate,
-VLEN (again, offset by one), which is 6 bits in length, and the same
-value stored in scalar register VLdest (if that register is nonzero).
-A value of 0b000000 will set MAXVL=VL=1, a value of 0b000001 will
-set MAXVL=VL= 2 and so on.
-
-This option will typically not be used so much for loops as it will be
+Modes 0b00 and 0b10 will typically not be used so much for loops as they will be
 for one-off instructions such as saving the entire register file to the
 stack with a single one-off Vectorised and predicated LD/ST, or as a way
 to save or restore registers in a function call with a single instruction.
 
-Notes:
+Unlike in RVV, VL is set (within the limits of MVL) to exactly the value requested, specifically so that LD/ST-MULTI style behaviour can be done in a single instruction.
+
+# VBLOCK Prefix
 
 * Bit 7 specifies if the prefix block format is the full 16 bit format
   (1) or the compact less expressive format (0). In the 8 bit format,
@@ -62,10 +55,10 @@ Notes:
   of entries are needed the last may be set to 0x00, indicating "unused".
 * Bit 15 specifies if the VL Block is present. If set to 1, the VL Block
   immediately follows the VBLOCK instruction Prefix
-* Bits 8 and 9 define how many RegCam entries (0 to 3 if bit 15 is 1,
-  otherwise 0 to 6) follow the (optional) VL Block.
-* Bits 10 and 11 define how many PredCam entries (0 to 3 if bit 7 is 1,
-  otherwise 0 to 6) follow the (optional) RegCam entries
+* Bits 8 and 9 define how many RegCam entries (0,1,2,4 if bit 15 is 1,
+  otherwise 0,2,4,8) follow the (optional) VL Block.
+* Bits 10 and 11 define how many PredCam entries (0,1,2,4 if bit 7 is 1,
+  otherwise 0,2,4,8) follow the (optional) RegCam entries
 * Bits 14 to 12 (IL) define the actual length of the instruction: total
   number of bits is 80 + 16 times IL.  Standard RV32, RVC and also
   SVPrefix (P48/64-\*-Type) instructions fit into this space, after the