From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 20 May 2020 14:23:42 +0000 (+0100)
Subject: whitespace, rename ilang to alu_main_stage.il
X-Git-Tag: div_pipeline~1037
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c1e619359c76295dd98b3ed1faecf41e7cb5c4e;p=soc.git

whitespace, rename ilang to alu_main_stage.il
---

diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index c139cccb..3bc06e6f 100644
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -70,7 +70,7 @@ class Driver(Elaboratable):
         # main assertion of arithmetic operations
         with m.Switch(rec.insn_type):
             with m.Case(InternalOp.OP_ADD):
-                
+
                 comb += Assert(Cat(o, carry_out) == (a + b + carry_in))
 
                 # CA32
@@ -104,7 +104,7 @@ class ALUTestCase(FHDLTestCase):
     def test_ilang(self):
         dut = Driver()
         vl = rtlil.convert(dut, ports=[])
-        with open("main_stage.il", "w") as f:
+        with open("alu_main_stage.il", "w") as f:
             f.write(vl)