From: Luke Kenneth Casson Leighton Date: Sun, 1 Mar 2020 20:19:39 +0000 (+0000) Subject: redo minor 19 table to not need "is valid" X-Git-Tag: convert-csv-opcode-to-binary~3250 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c1fdd70ebf515c7c831afb77b83a5258e8530d7;p=libreriscv.git redo minor 19 table to not need "is valid" --- diff --git a/openpower/isatables/minor_19.csv b/openpower/isatables/minor_19.csv index 9ad5acad0..7f32aa3f7 100644 --- a/openpower/isatables/minor_19.csv +++ b/openpower/isatables/minor_19.csv @@ -1,5 +1,15 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment -0b000,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mcrf; and cr logical ops -0b001,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,add pcis not implemented yet -0b100,ALU,OP_BCREG,SPR,SPR,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr bcctr bctar -0b111,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync +0000000000,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mcrf +0100000001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crand +0010000001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crandc +0100100001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,creqv +0011100001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnand +0000100001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crnor +0111000001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,cror +0110100001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crorc +0110000001,ALU,OP_MCRF,NONE,NONE,NONE,NONE,1,1,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crxor +-----00010,ALU,OP_ILLEGAL,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,1,add pcis not implemented yet +1000010000,ALU,OP_BCREG,SPR,SPR,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bcctr +0000010000,ALU,OP_BCREG,SPR,SPR,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr +1000110000,ALU,OP_BCREG,SPR,SPR,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bctar +0010010110,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync