From: Henner Zeller <h.zeller@acm.org>
Date: Sun, 29 Sep 2019 07:17:40 +0000 (-0700)
Subject: Avoid work in replace() if rules empty.
X-Git-Tag: working-ls180~1038^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c2b4f0a50678f949418b7b7329550615fadde83;p=yosys.git

Avoid work in replace() if rules empty.

This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1d380135b..17be28f78 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
 	log_assert(other != NULL);
 	log_assert(width_ == other->width_);
 
+	if (rules.empty()) return;
 	unpack();
 	other->unpack();
 
@@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
 	log_assert(other != NULL);
 	log_assert(width_ == other->width_);
 
+	if (rules.empty()) return;
 	unpack();
 	other->unpack();