From: lkcl <lkcl@web>
Date: Sat, 8 Apr 2023 09:39:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~82
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c2dc4e18dfb0a93eeb5341678f7e555e284911e;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn
index 43955ffd8..25deae8bd 100644
--- a/openpower/sv/rfc/ls012.mdwn
+++ b/openpower/sv/rfc/ls012.mdwn
@@ -89,6 +89,22 @@ the usual cascading-option-multipliers (SIMD width, bitwidth, saturation, HI/LO)
 are abstracted out to RISC-paradigm Prefixing, leaving just absolute-diff-accumulate,
 min-max, average-add etc. as "basic primitives".
 
+## Twin-Butterfly FFT/DCT/DFT for DSP/HPC/AI/AV
+
+The number of uses in Computer Science for DCT, NTT, FFT and DFT, is astonishing.
+The wikipedia page lists over a hundred separate and distinct areas: Audio, Video,
+Radar, Baseband processing, AI, Solomon-Reed Error Correction, the list goes on and on.
+ARM has special dedicated Integer Twin-butterfly instructions. TI's MSP Series DSPs
+have had FFT Inner loop support for over 30 years. Qualcomm's Hexagon VLIW Baseband
+DSP can do full FFT triple loops in one VLIW group.
+
+It should be pretty clear this is high priority.
+
+With SVP64  [[sv/remap]] providing the Loop Schedules it falls to the Scalar side of
+the ISA to add the prerequisite "Twin Butterfly" operations, typically performing
+for example one multiply but in-place subtracting that product from one operand and
+adding it to the other.  The *in-place* aspect is strategically extremely important
+for significant reductions in Vectorised register usage, particularly for DCT.
 
 [[!inline pages="openpower/sv/rfc/ls012/areas.mdwn" raw=yes ]]