From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 13 Jun 2018 14:09:52 +0000 (+0100)
Subject: cross-reference issues under consideration
X-Git-Tag: convert-csv-opcode-to-binary~5214
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c2ef0c0b88be360b5e0a782ec0056cc12ac8908;p=libreriscv.git

cross-reference issues under consideration
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 803bdba02..4cf0937ed 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1059,7 +1059,7 @@ Similar rules apply to the destination register.
 * Throw an exception.  Whether that actually results in spawning threads
   as part of the trap-handling remains to be seen.
 
-# Under consideration
+# Under consideration <a name="issues"></a>
 
 From the Chennai 2018 slides the following issues were raised.
 Efforts to analyse and answer these questions are below.
diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 417c0f3d9..82d9b1d36 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -715,6 +715,7 @@ loop:
    \item 8/16-bit ops is it worthwhile adding a "start offset"? \\
          (a bit like misaligned addressing... for registers)\\
          or just use predication to skip start?
+   \item http://libre-riscv.org/simple\_v\_extension/\#issues
   \end{itemize}
 }