From: whitequark <whitequark@whitequark.org>
Date: Wed, 11 Sep 2019 23:35:43 +0000 (+0000)
Subject: build.plat,vendor: allow clock constraints on arbitrary signals.
X-Git-Tag: v0.1rc1~114
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c30147e39ccc19294ab2d62888dc1e70b0672b5;p=nmigen.git

build.plat,vendor: allow clock constraints on arbitrary signals.

Currently only done for Synopsys based toolchains (i.e. not nextpnr).

Refs #88.
---

diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py
index f6aac54..c8e5058 100644
--- a/nmigen/build/plat.py
+++ b/nmigen/build/plat.py
@@ -296,6 +296,9 @@ class TemplatedPlatform(Platform):
             else:
                 return " ".join(opts)
 
+        def hierarchy(signal, separator):
+            return separator.join(name_map[signal][1:])
+
         def verbose(arg):
             if "NMIGEN_verbose" in os.environ:
                 return arg
@@ -313,6 +316,7 @@ class TemplatedPlatform(Platform):
                 source   = textwrap.dedent(source).strip()
                 compiled = jinja2.Template(source, trim_blocks=True, lstrip_blocks=True)
                 compiled.environment.filters["options"] = options
+                compiled.environment.filters["hierarchy"] = hierarchy
             except jinja2.TemplateSyntaxError as e:
                 e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),)
                 raise
diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index a2231a1..db4ac06 100644
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -209,7 +209,7 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.sdc": r"""
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                create_clock -period {{1000000000/frequency}} [get_ports {{signal.name}}]
+                create_clock -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """,
diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 9529597..61733c8 100644
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -106,7 +106,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
                 {% endfor %}
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_ports {{signal.name}}]
+                create_clock -name {{signal.name}} -period {{1000000000/frequency}} [get_nets {{signal|hierarchy("/")}}]
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """
diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 9f152dc..c4c18ce 100644
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -127,8 +127,8 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
                 {% endfor %}
             {% endfor %}
             {% for signal, frequency in platform.iter_clock_constraints() -%}
-                NET "{{signal.name}}" TNM_NET="PRD{{signal.name}}";
-                TIMESPEC "TS{{signal.name}}"=PERIOD "PRD{{signal.name}}" {{1000000000/frequency}} ns HIGH 50%;
+                NET "{{signal|hierarchy("/")}}" TNM_NET="PRD{{signal|hierarchy("/")}}";
+                TIMESPEC "TS{{signal|hierarchy("/")}}"=PERIOD "PRD{{signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
             {% endfor %}
             {{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
         """