From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 17:29:43 +0000 (+0000)
Subject: whoops, must use dest bitwidth on mulhsu
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c37d208b7e9ff5ab3441627abd91b1bad6ddb1f;p=riscv-isa-sim.git

whoops, must use dest bitwidth on mulhsu
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index bf78ba9..6de7ea9 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -605,15 +605,15 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
 /* 32-bit mulh/mulhu/mulhsu */
 sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
+    // normally the result is shuffled down by 32 bits (elwidth==default)
+    // however with variable bitwidth we want the top elwidth bits.
+    // so, get the destination bitwidth first...
+    reg_t reg = _insn->rd().reg;
+    uint8_t dest_elwidth = _insn->reg_elwidth(reg, true);
+    uint8_t bitwidth = get_bitwidth(dest_elwidth, xlen);
     sv_reg_t m = rv_mul(lhs, rhs);
-    uint8_t bitwidth = get_bitwidth(m.get_elwidth(), xlen);
     uint64_t result = (uint64_t)m;
     result >>= std::min(bitwidth, (uint8_t)32);
-    if (_insn->signextended) {
-        result = sext_bwid(result, bitwidth);
-    } else {
-        result = zext_bwid(result, bitwidth);
-    }
     return sv_reg_t(result, xlen, bitwidth);
 }