From: Sebastien Bourdeauducq Date: Mon, 15 Jul 2013 19:34:53 +0000 (+0200) Subject: tb/lasmicon: add DF test X-Git-Tag: 24jan2021_ls180~2863 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c44c7249996eed743ea7887d3047735b14c2d3e;p=litex.git tb/lasmicon: add DF test --- diff --git a/tb/lasmicon/lasmicon_df.py b/tb/lasmicon/lasmicon_df.py new file mode 100644 index 00000000..054e1b66 --- /dev/null +++ b/tb/lasmicon/lasmicon_df.py @@ -0,0 +1,43 @@ +from migen.fhdl.std import * +from migen.bus import lasmibus +from migen.actorlib import dma_lasmi +from migen.sim.generic import Simulator, TopLevel, Proxy + +from milkymist.lasmicon import * + +from common import sdram_phy, sdram_geom, sdram_timing, DFILogger + +class TB(Module): + def __init__(self): + self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing) + # FIXME: remove dummy master + self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], 2, self.ctler.nrowbits) + self.submodules.logger = DFILogger(self.ctler.dfi) + self.submodules.writer = dma_lasmi.Writer(self.xbar.masters[0]) + + self.comb += self.writer.address_data.stb.eq(1) + pl = self.writer.address_data.payload + pl.a.reset = 255 + pl.d.reset = pl.a.reset*2 + self.sync += If(self.writer.address_data.ack, + pl.a.eq(pl.a + 1), + pl.d.eq(pl.d + 2) + ) + self.open_row = None + + def do_simulation(self, s): + dfip = Proxy(s, self.ctler.dfi) + for p in dfip.phases: + if p.ras_n and not p.cas_n and not p.we_n: # write + d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64) + print(d) + if d != p.address//2 + p.bank*512 + self.open_row*2048: + print("**** ERROR ****") + elif not p.ras_n and p.cas_n and p.we_n: # activate + self.open_row = p.address + +def main(): + sim = Simulator(TB(), TopLevel("my.vcd")) + sim.run(3500) + +main()