From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 3 Jan 2020 09:13:31 +0000 (+0100)
Subject: Arm64: correct uzp{1,2} mnemonics
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c45011acd7a589c306e74563d00fb3fa5c14bbd;p=binutils-gdb.git

Arm64: correct uzp{1,2} mnemonics

According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 933c17e6036..8a6470f4c6d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+	* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
+	* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
+
 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 
 	* testsuite/gas/aarch64/f64mm.d,
diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d
index b2aa86132ac..e9ec69440ab 100644
--- a/gas/testsuite/gas/aarch64/f64mm.d
+++ b/gas/testsuite/gas/aarch64/f64mm.d
@@ -52,10 +52,10 @@ Disassembly of section \.text:
  *[0-9a-f]+:	05a00000 	zip1	z0\.q, z0\.q, z0\.q
  *[0-9a-f]+:	05a506b1 	zip2	z17\.q, z21\.q, z5\.q
  *[0-9a-f]+:	05a00400 	zip2	z0\.q, z0\.q, z0\.q
- *[0-9a-f]+:	05a50ab1 	uzip1	z17\.q, z21\.q, z5\.q
- *[0-9a-f]+:	05a00800 	uzip1	z0\.q, z0\.q, z0\.q
- *[0-9a-f]+:	05a50eb1 	uzip2	z17\.q, z21\.q, z5\.q
- *[0-9a-f]+:	05a00c00 	uzip2	z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+:	05a50ab1 	uzp1	z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+:	05a00800 	uzp1	z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+:	05a50eb1 	uzp2	z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+:	05a00c00 	uzp2	z0\.q, z0\.q, z0\.q
  *[0-9a-f]+:	05a51ab1 	trn1	z17\.q, z21\.q, z5\.q
  *[0-9a-f]+:	05a01800 	trn1	z0\.q, z0\.q, z0\.q
  *[0-9a-f]+:	05a51eb1 	trn2	z17\.q, z21\.q, z5\.q
diff --git a/gas/testsuite/gas/aarch64/f64mm.s b/gas/testsuite/gas/aarch64/f64mm.s
index fcf662be300..cfe6b176d24 100644
--- a/gas/testsuite/gas/aarch64/f64mm.s
+++ b/gas/testsuite/gas/aarch64/f64mm.s
@@ -60,10 +60,10 @@ zip1 z0.q, z0.q, z0.q
 zip2 z17.q, z21.q, z5.q
 zip2 z0.q, z0.q, z0.q
 
-uzip1 z17.q, z21.q, z5.q
-uzip1 z0.q, z0.q, z0.q
-uzip2 z17.q, z21.q, z5.q
-uzip2 z0.q, z0.q, z0.q
+uzp1 z17.q, z21.q, z5.q
+uzp1 z0.q, z0.q, z0.q
+uzp2 z17.q, z21.q, z5.q
+uzp2 z0.q, z0.q, z0.q
 
 trn1 z17.q, z21.q, z5.q
 trn1 z0.q, z0.q, z0.q
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bf031a76d80..ec6451271c9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2020-01-03  Jan Beulich  <jbeulich@suse.com>
+
+	* opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
+	uzip{1,2}.
+	* opcodes/aarch64-dis-2.c: Re-generate.
+
 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 
 	* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 950a5f2e99b..23f32e9478e 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -9913,7 +9913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                                   /* 33222222222211111111110000000000
                                                                      10987654321098765432109876543210
                                                                      000001x1101xxxxx000010xxxxxxxxxx
-                                                                     uzip1.  */
+                                                                     uzp1.  */
                                                                   return 2409;
                                                                 }
                                                               else
@@ -9943,7 +9943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                                   /* 33222222222211111111110000000000
                                                                      10987654321098765432109876543210
                                                                      000001x1101xxxxx000011xxxxxxxxxx
-                                                                     uzip2.  */
+                                                                     uzp2.  */
                                                                   return 2410;
                                                                 }
                                                               else
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8a74777eedb..3128d841302 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5084,8 +5084,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
   F64MATMUL_SVE_INSN ("ld1rod",  0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
   F64MATMUL_SVE_INSN ("zip1",    0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
   F64MATMUL_SVE_INSN ("zip2",    0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-  F64MATMUL_SVE_INSN ("uzip1",   0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-  F64MATMUL_SVE_INSN ("uzip2",   0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+  F64MATMUL_SVE_INSN ("uzp1",    0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+  F64MATMUL_SVE_INSN ("uzp2",    0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
   F64MATMUL_SVE_INSN ("trn1",    0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
   F64MATMUL_SVE_INSN ("trn2",    0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
   /* Matrix Multiply advanced SIMD instructions.  */