From: Jose E. Marchesi Date: Tue, 4 Aug 2020 16:11:31 +0000 (+0200) Subject: sim: generated files for the eBPF simulator X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c4c18181ea382adf407df235c7991feb0647bab;p=binutils-gdb.git sim: generated files for the eBPF simulator This patch adds the CGEN generated files for the eBPF simulator. sim/ChangeLog: 2020-08-04 Jose E. Marchesi David Faust * bpf/arch.c: Likewise. * bpf/arch.h: Likewise. * bpf/cpu.c: Likewise. * bpf/cpu.h: Likewise. * bpf/cpuall.h: Likewise. * bpf/decode-be.c: Likewise. * bpf/decode-be.h: Likewise. * bpf/decode-le.c: Likewise. * bpf/decode-le.h: Likewise. * bpf/defs-be.h: Likewise. * bpf/defs-le.h: Likewise. * bpf/sem-be.c: Likewise. * bpf/sem-le.c: Likewise. --- diff --git a/sim/ChangeLog b/sim/ChangeLog index d1816165488..5316e248266 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,20 @@ +2020-08-04 Jose E. Marchesi + David Faust + + * bpf/arch.c: Likewise. + * bpf/arch.h: Likewise. + * bpf/cpu.c: Likewise. + * bpf/cpu.h: Likewise. + * bpf/cpuall.h: Likewise. + * bpf/decode-be.c: Likewise. + * bpf/decode-be.h: Likewise. + * bpf/decode-le.c: Likewise. + * bpf/decode-le.h: Likewise. + * bpf/defs-be.h: Likewise. + * bpf/defs-le.h: Likewise. + * bpf/sem-be.c: Likewise. + * bpf/sem-le.c: Likewise. + 2020-08-04 Jose E. Marchesi David Faust diff --git a/sim/bpf/arch.c b/sim/bpf/arch.c new file mode 100644 index 00000000000..d4b6d139c5b --- /dev/null +++ b/sim/bpf/arch.c @@ -0,0 +1,35 @@ +/* Simulator support for bpf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sim-main.h" +#include "bfd.h" + +const SIM_MACH *sim_machs[] = +{ +#ifdef HAVE_CPU_BPFBF + & bpf_mach, +#endif + 0 +}; + diff --git a/sim/bpf/arch.h b/sim/bpf/arch.h new file mode 100644 index 00000000000..734d65398fc --- /dev/null +++ b/sim/bpf/arch.h @@ -0,0 +1,50 @@ +/* Simulator header for bpf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef BPF_ARCH_H +#define BPF_ARCH_H + +#define TARGET_BIG_ENDIAN 1 + +#define WI DI +#define UWI UDI +#define AI UDI + +#define IAI UDI + +/* Enum declaration for model types. */ +typedef enum model_type { + MODEL_BPF_DEF, MODEL_MAX +} MODEL_TYPE; + +#define MAX_MODELS ((int) MODEL_MAX) + +/* Enum declaration for unit types. */ +typedef enum unit_type { + UNIT_NONE, UNIT_BPF_DEF_U_EXEC, UNIT_MAX +} UNIT_TYPE; + +#define MAX_UNITS (1) + +#endif /* BPF_ARCH_H */ diff --git a/sim/bpf/cpu.c b/sim/bpf/cpu.c new file mode 100644 index 00000000000..c19de5d8e1f --- /dev/null +++ b/sim/bpf/cpu.c @@ -0,0 +1,69 @@ +/* Misc. support for CPU family bpfbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#define WANT_CPU bpfbf +#define WANT_CPU_BPFBF + +#include "sim-main.h" +#include "cgen-ops.h" + +/* Get the value of h-gpr. */ + +DI +bpfbf_h_gpr_get (SIM_CPU *current_cpu, UINT regno) +{ + return CPU (h_gpr[regno]); +} + +/* Set a value for h-gpr. */ + +void +bpfbf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, DI newval) +{ + CPU (h_gpr[regno]) = newval; +} + +/* Get the value of h-pc. */ + +UDI +bpfbf_h_pc_get (SIM_CPU *current_cpu) +{ + return GET_H_PC (); +} + +/* Set a value for h-pc. */ + +void +bpfbf_h_pc_set (SIM_CPU *current_cpu, UDI newval) +{ + SET_H_PC (newval); +} + +/* Record trace results for INSN. */ + +void +bpfbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn, + int *indices, TRACE_RECORD *tr) +{ +} diff --git a/sim/bpf/cpu.h b/sim/bpf/cpu.h new file mode 100644 index 00000000000..1e23fbeabf5 --- /dev/null +++ b/sim/bpf/cpu.h @@ -0,0 +1,81 @@ +/* CPU family header for bpfbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef CPU_BPFBF_H +#define CPU_BPFBF_H + +/* Maximum number of instructions that are fetched at a time. + This is for LIW type instructions sets (e.g. m32r). */ +#define MAX_LIW_INSNS 1 + +/* Maximum number of instructions that can be executed in parallel. */ +#define MAX_PARALLEL_INSNS 1 + +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_LGUINT CGEN_INSN_WORD; + +#include "cgen-engine.h" + +/* CPU state information. */ +typedef struct { + /* Hardware elements. */ + struct { + /* General Purpose Registers */ + DI h_gpr[16]; +#define GET_H_GPR(a1) CPU (h_gpr)[a1] +#define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x)) + /* program counter */ + UDI h_pc; +#define GET_H_PC() CPU (h_pc) +#define SET_H_PC(x) \ +do { \ +CPU (h_pc) = (x);\ +;} while (0) + } hardware; +#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +} BPFBF_CPU_DATA; + +/* Cover fns for register access. */ +DI bpfbf_h_gpr_get (SIM_CPU *, UINT); +void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI); +UDI bpfbf_h_pc_get (SIM_CPU *); +void bpfbf_h_pc_set (SIM_CPU *, UDI); + +/* These must be hand-written. */ +extern CPUREG_FETCH_FN bpfbf_fetch_register; +extern CPUREG_STORE_FN bpfbf_store_register; + +typedef struct { + int empty; +} MODEL_BPF_DEF_DATA; + +/* Collection of various things for the trace handler to use. */ + +typedef struct trace_record { + IADDR pc; + /* FIXME:wip */ +} TRACE_RECORD; + +#endif /* CPU_BPFBF_H */ diff --git a/sim/bpf/cpuall.h b/sim/bpf/cpuall.h new file mode 100644 index 00000000000..3933dea3539 --- /dev/null +++ b/sim/bpf/cpuall.h @@ -0,0 +1,65 @@ +/* Simulator CPU header for bpf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef BPF_CPUALL_H +#define BPF_CPUALL_H + +/* Include files for each cpu family. */ + +#ifdef WANT_CPU_BPFBF +#include "eng.h" +#include "cpu.h" +#include "decode.h" +#endif + +extern const SIM_MACH bpf_mach; + +#ifndef WANT_CPU +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ +}; +#endif + +#ifndef WANT_CPU +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; +#endif + +#endif /* BPF_CPUALL_H */ diff --git a/sim/bpf/decode-be.c b/sim/bpf/decode-be.c new file mode 100644 index 00000000000..22d95ddec1f --- /dev/null +++ b/sim/bpf/decode-be.c @@ -0,0 +1,1129 @@ +/* Simulator instruction decoder for bpfbf_ebpfbe. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#define WANT_CPU bpfbf +#define WANT_CPU_BPFBF + +#include "sim-main.h" +#include "sim-assert.h" + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC bpfbf_ebpfbe_insn_data[BPFBF_EBPFBE_INSN__MAX]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem bpfbf_ebpfbe_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, BPFBF_EBPFBE_INSN_X_CTI_CHAIN, BPFBF_EBPFBE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_SFMT_EMPTY }, + { BPF_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ADDRBE, BPFBF_EBPFBE_INSN_ADDRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_SUBRBE, BPFBF_EBPFBE_INSN_SUBRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_MULRBE, BPFBF_EBPFBE_INSN_MULRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_DIVRBE, BPFBF_EBPFBE_INSN_DIVRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ORRBE, BPFBF_EBPFBE_INSN_ORRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_OR32RBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ANDRBE, BPFBF_EBPFBE_INSN_ANDRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_AND32RBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_LSHRBE, BPFBF_EBPFBE_INSN_LSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_RSHRBE, BPFBF_EBPFBE_INSN_RSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_MODRBE, BPFBF_EBPFBE_INSN_MODRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_XORRBE, BPFBF_EBPFBE_INSN_XORRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ARSHRBE, BPFBF_EBPFBE_INSN_ARSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE }, + { BPF_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE }, + { BPF_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_SFMT_NEGBE }, + { BPF_INSN_NEG32BE, BPFBF_EBPFBE_INSN_NEG32BE, BPFBF_EBPFBE_SFMT_NEGBE }, + { BPF_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_SFMT_MOVIBE }, + { BPF_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_SFMT_MOVRBE }, + { BPF_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_SFMT_MOVIBE }, + { BPF_INSN_MOV32RBE, BPFBF_EBPFBE_INSN_MOV32RBE, BPFBF_EBPFBE_SFMT_MOVRBE }, + { BPF_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_SFMT_ENDLEBE }, + { BPF_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_SFMT_ENDLEBE }, + { BPF_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_SFMT_LDDWBE }, + { BPF_INSN_LDABSW, BPFBF_EBPFBE_INSN_LDABSW, BPFBF_EBPFBE_SFMT_LDABSW }, + { BPF_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_SFMT_LDABSH }, + { BPF_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_SFMT_LDABSB }, + { BPF_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_SFMT_LDABSDW }, + { BPF_INSN_LDINDWBE, BPFBF_EBPFBE_INSN_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDWBE }, + { BPF_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDHBE }, + { BPF_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDBBE }, + { BPF_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_SFMT_LDINDDWBE }, + { BPF_INSN_LDXWBE, BPFBF_EBPFBE_INSN_LDXWBE, BPFBF_EBPFBE_SFMT_LDXWBE }, + { BPF_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_SFMT_LDXHBE }, + { BPF_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_SFMT_LDXBBE }, + { BPF_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_SFMT_LDXDWBE }, + { BPF_INSN_STXWBE, BPFBF_EBPFBE_INSN_STXWBE, BPFBF_EBPFBE_SFMT_STXWBE }, + { BPF_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_SFMT_STXHBE }, + { BPF_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_SFMT_STXBBE }, + { BPF_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_SFMT_STXDWBE }, + { BPF_INSN_STBBE, BPFBF_EBPFBE_INSN_STBBE, BPFBF_EBPFBE_SFMT_STBBE }, + { BPF_INSN_STHBE, BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_SFMT_STHBE }, + { BPF_INSN_STWBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_SFMT_STWBE }, + { BPF_INSN_STDWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_SFMT_STDWBE }, + { BPF_INSN_JEQIBE, BPFBF_EBPFBE_INSN_JEQIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JGTIBE, BPFBF_EBPFBE_INSN_JGTIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JGEIBE, BPFBF_EBPFBE_INSN_JGEIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JLTIBE, BPFBF_EBPFBE_INSN_JLTIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JLEIBE, BPFBF_EBPFBE_INSN_JLEIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSETIBE, BPFBF_EBPFBE_INSN_JSETIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JNEIBE, BPFBF_EBPFBE_INSN_JNEIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSGTIBE, BPFBF_EBPFBE_INSN_JSGTIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSGEIBE, BPFBF_EBPFBE_INSN_JSGEIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSLTIBE, BPFBF_EBPFBE_INSN_JSLTIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSLEIBE, BPFBF_EBPFBE_INSN_JSLEIBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE }, + { BPF_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE }, + { BPF_INSN_CALLBE, BPFBF_EBPFBE_INSN_CALLBE, BPFBF_EBPFBE_SFMT_CALLBE }, + { BPF_INSN_JA, BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_SFMT_JA }, + { BPF_INSN_EXIT, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_SFMT_EXIT }, + { BPF_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDDWBE }, + { BPF_INSN_XADDWBE, BPFBF_EBPFBE_INSN_XADDWBE, BPFBF_EBPFBE_SFMT_XADDWBE }, + { BPF_INSN_BRKPT, BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_SFMT_EXIT }, +}; + +static const struct insn_sem bpfbf_ebpfbe_insn_sem_invalid = +{ + VIRTUAL_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_SFMT_EMPTY +}; + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif + + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +bpfbf_ebpfbe_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = BPFBF_EBPFBE_INSN__MAX; + IDESC *table = bpfbf_ebpfbe_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & bpfbf_ebpfbe_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = bpfbf_ebpfbe_insn_sem, tend = t + sizeof (bpfbf_ebpfbe_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +bpfbf_ebpfbe_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_WORD base_insn, + ARGBUF *abuf) +{ + /* Result of decoder. */ + BPFBF_EBPFBE_INSN_TYPE itype; + + { + CGEN_INSN_WORD insn = base_insn; + + { + unsigned int val = (((insn >> 0) & (255 << 0))); + switch (val) + { + case 4 : itype = BPFBF_EBPFBE_INSN_ADD32IBE; goto extract_sfmt_addibe; + case 5 : itype = BPFBF_EBPFBE_INSN_JA; goto extract_sfmt_ja; + case 7 : itype = BPFBF_EBPFBE_INSN_ADDIBE; goto extract_sfmt_addibe; + case 12 : itype = BPFBF_EBPFBE_INSN_ADD32RBE; goto extract_sfmt_addrbe; + case 15 : itype = BPFBF_EBPFBE_INSN_ADDRBE; goto extract_sfmt_addrbe; + case 20 : itype = BPFBF_EBPFBE_INSN_SUB32IBE; goto extract_sfmt_addibe; + case 21 : itype = BPFBF_EBPFBE_INSN_JEQIBE; goto extract_sfmt_jeqibe; + case 22 : itype = BPFBF_EBPFBE_INSN_JEQ32IBE; goto extract_sfmt_jeqibe; + case 23 : itype = BPFBF_EBPFBE_INSN_SUBIBE; goto extract_sfmt_addibe; + case 24 : itype = BPFBF_EBPFBE_INSN_LDDWBE; goto extract_sfmt_lddwbe; + case 28 : itype = BPFBF_EBPFBE_INSN_SUB32RBE; goto extract_sfmt_addrbe; + case 29 : itype = BPFBF_EBPFBE_INSN_JEQRBE; goto extract_sfmt_jeqrbe; + case 30 : itype = BPFBF_EBPFBE_INSN_JEQ32RBE; goto extract_sfmt_jeqrbe; + case 31 : itype = BPFBF_EBPFBE_INSN_SUBRBE; goto extract_sfmt_addrbe; + case 32 : itype = BPFBF_EBPFBE_INSN_LDABSW; goto extract_sfmt_ldabsw; + case 36 : itype = BPFBF_EBPFBE_INSN_MUL32IBE; goto extract_sfmt_addibe; + case 37 : itype = BPFBF_EBPFBE_INSN_JGTIBE; goto extract_sfmt_jeqibe; + case 38 : itype = BPFBF_EBPFBE_INSN_JGT32IBE; goto extract_sfmt_jeqibe; + case 39 : itype = BPFBF_EBPFBE_INSN_MULIBE; goto extract_sfmt_addibe; + case 40 : itype = BPFBF_EBPFBE_INSN_LDABSH; goto extract_sfmt_ldabsh; + case 44 : itype = BPFBF_EBPFBE_INSN_MUL32RBE; goto extract_sfmt_addrbe; + case 45 : itype = BPFBF_EBPFBE_INSN_JGTRBE; goto extract_sfmt_jeqrbe; + case 46 : itype = BPFBF_EBPFBE_INSN_JGT32RBE; goto extract_sfmt_jeqrbe; + case 47 : itype = BPFBF_EBPFBE_INSN_MULRBE; goto extract_sfmt_addrbe; + case 48 : itype = BPFBF_EBPFBE_INSN_LDABSB; goto extract_sfmt_ldabsb; + case 52 : itype = BPFBF_EBPFBE_INSN_DIV32IBE; goto extract_sfmt_addibe; + case 53 : itype = BPFBF_EBPFBE_INSN_JGEIBE; goto extract_sfmt_jeqibe; + case 54 : itype = BPFBF_EBPFBE_INSN_JGE32IBE; goto extract_sfmt_jeqibe; + case 55 : itype = BPFBF_EBPFBE_INSN_DIVIBE; goto extract_sfmt_addibe; + case 56 : itype = BPFBF_EBPFBE_INSN_LDABSDW; goto extract_sfmt_ldabsdw; + case 60 : itype = BPFBF_EBPFBE_INSN_DIV32RBE; goto extract_sfmt_addrbe; + case 61 : itype = BPFBF_EBPFBE_INSN_JGERBE; goto extract_sfmt_jeqrbe; + case 62 : itype = BPFBF_EBPFBE_INSN_JGE32RBE; goto extract_sfmt_jeqrbe; + case 63 : itype = BPFBF_EBPFBE_INSN_DIVRBE; goto extract_sfmt_addrbe; + case 64 : itype = BPFBF_EBPFBE_INSN_LDINDWBE; goto extract_sfmt_ldindwbe; + case 68 : itype = BPFBF_EBPFBE_INSN_OR32IBE; goto extract_sfmt_addibe; + case 69 : itype = BPFBF_EBPFBE_INSN_JSETIBE; goto extract_sfmt_jeqibe; + case 70 : itype = BPFBF_EBPFBE_INSN_JSET32IBE; goto extract_sfmt_jeqibe; + case 71 : itype = BPFBF_EBPFBE_INSN_ORIBE; goto extract_sfmt_addibe; + case 72 : itype = BPFBF_EBPFBE_INSN_LDINDHBE; goto extract_sfmt_ldindhbe; + case 76 : itype = BPFBF_EBPFBE_INSN_OR32RBE; goto extract_sfmt_addrbe; + case 77 : itype = BPFBF_EBPFBE_INSN_JSETRBE; goto extract_sfmt_jeqrbe; + case 78 : itype = BPFBF_EBPFBE_INSN_JSET32RBE; goto extract_sfmt_jeqrbe; + case 79 : itype = BPFBF_EBPFBE_INSN_ORRBE; goto extract_sfmt_addrbe; + case 80 : itype = BPFBF_EBPFBE_INSN_LDINDBBE; goto extract_sfmt_ldindbbe; + case 84 : itype = BPFBF_EBPFBE_INSN_AND32IBE; goto extract_sfmt_addibe; + case 85 : itype = BPFBF_EBPFBE_INSN_JNEIBE; goto extract_sfmt_jeqibe; + case 86 : itype = BPFBF_EBPFBE_INSN_JNE32IBE; goto extract_sfmt_jeqibe; + case 87 : itype = BPFBF_EBPFBE_INSN_ANDIBE; goto extract_sfmt_addibe; + case 88 : itype = BPFBF_EBPFBE_INSN_LDINDDWBE; goto extract_sfmt_ldinddwbe; + case 92 : itype = BPFBF_EBPFBE_INSN_AND32RBE; goto extract_sfmt_addrbe; + case 93 : itype = BPFBF_EBPFBE_INSN_JNERBE; goto extract_sfmt_jeqrbe; + case 94 : itype = BPFBF_EBPFBE_INSN_JNE32RBE; goto extract_sfmt_jeqrbe; + case 95 : itype = BPFBF_EBPFBE_INSN_ANDRBE; goto extract_sfmt_addrbe; + case 97 : itype = BPFBF_EBPFBE_INSN_LDXWBE; goto extract_sfmt_ldxwbe; + case 98 : itype = BPFBF_EBPFBE_INSN_STWBE; goto extract_sfmt_stwbe; + case 99 : itype = BPFBF_EBPFBE_INSN_STXWBE; goto extract_sfmt_stxwbe; + case 100 : itype = BPFBF_EBPFBE_INSN_LSH32IBE; goto extract_sfmt_addibe; + case 101 : itype = BPFBF_EBPFBE_INSN_JSGTIBE; goto extract_sfmt_jeqibe; + case 102 : itype = BPFBF_EBPFBE_INSN_JSGT32IBE; goto extract_sfmt_jeqibe; + case 103 : itype = BPFBF_EBPFBE_INSN_LSHIBE; goto extract_sfmt_addibe; + case 105 : itype = BPFBF_EBPFBE_INSN_LDXHBE; goto extract_sfmt_ldxhbe; + case 106 : itype = BPFBF_EBPFBE_INSN_STHBE; goto extract_sfmt_sthbe; + case 107 : itype = BPFBF_EBPFBE_INSN_STXHBE; goto extract_sfmt_stxhbe; + case 108 : itype = BPFBF_EBPFBE_INSN_LSH32RBE; goto extract_sfmt_addrbe; + case 109 : itype = BPFBF_EBPFBE_INSN_JSGTRBE; goto extract_sfmt_jeqrbe; + case 110 : itype = BPFBF_EBPFBE_INSN_JSGT32RBE; goto extract_sfmt_jeqrbe; + case 111 : itype = BPFBF_EBPFBE_INSN_LSHRBE; goto extract_sfmt_addrbe; + case 113 : itype = BPFBF_EBPFBE_INSN_LDXBBE; goto extract_sfmt_ldxbbe; + case 114 : itype = BPFBF_EBPFBE_INSN_STBBE; goto extract_sfmt_stbbe; + case 115 : itype = BPFBF_EBPFBE_INSN_STXBBE; goto extract_sfmt_stxbbe; + case 116 : itype = BPFBF_EBPFBE_INSN_RSH32IBE; goto extract_sfmt_addibe; + case 117 : itype = BPFBF_EBPFBE_INSN_JSGEIBE; goto extract_sfmt_jeqibe; + case 118 : itype = BPFBF_EBPFBE_INSN_JSGE32IBE; goto extract_sfmt_jeqibe; + case 119 : itype = BPFBF_EBPFBE_INSN_RSHIBE; goto extract_sfmt_addibe; + case 121 : itype = BPFBF_EBPFBE_INSN_LDXDWBE; goto extract_sfmt_ldxdwbe; + case 122 : itype = BPFBF_EBPFBE_INSN_STDWBE; goto extract_sfmt_stdwbe; + case 123 : itype = BPFBF_EBPFBE_INSN_STXDWBE; goto extract_sfmt_stxdwbe; + case 124 : itype = BPFBF_EBPFBE_INSN_RSH32RBE; goto extract_sfmt_addrbe; + case 125 : itype = BPFBF_EBPFBE_INSN_JSGERBE; goto extract_sfmt_jeqrbe; + case 126 : itype = BPFBF_EBPFBE_INSN_JSGE32RBE; goto extract_sfmt_jeqrbe; + case 127 : itype = BPFBF_EBPFBE_INSN_RSHRBE; goto extract_sfmt_addrbe; + case 132 : itype = BPFBF_EBPFBE_INSN_NEG32BE; goto extract_sfmt_negbe; + case 133 : itype = BPFBF_EBPFBE_INSN_CALLBE; goto extract_sfmt_callbe; + case 135 : itype = BPFBF_EBPFBE_INSN_NEGBE; goto extract_sfmt_negbe; + case 140 : itype = BPFBF_EBPFBE_INSN_BRKPT; goto extract_sfmt_exit; + case 148 : itype = BPFBF_EBPFBE_INSN_MOD32IBE; goto extract_sfmt_addibe; + case 149 : itype = BPFBF_EBPFBE_INSN_EXIT; goto extract_sfmt_exit; + case 151 : itype = BPFBF_EBPFBE_INSN_MODIBE; goto extract_sfmt_addibe; + case 156 : itype = BPFBF_EBPFBE_INSN_MOD32RBE; goto extract_sfmt_addrbe; + case 159 : itype = BPFBF_EBPFBE_INSN_MODRBE; goto extract_sfmt_addrbe; + case 164 : itype = BPFBF_EBPFBE_INSN_XOR32IBE; goto extract_sfmt_addibe; + case 165 : itype = BPFBF_EBPFBE_INSN_JLTIBE; goto extract_sfmt_jeqibe; + case 166 : itype = BPFBF_EBPFBE_INSN_JLT32IBE; goto extract_sfmt_jeqibe; + case 167 : itype = BPFBF_EBPFBE_INSN_XORIBE; goto extract_sfmt_addibe; + case 172 : itype = BPFBF_EBPFBE_INSN_XOR32RBE; goto extract_sfmt_addrbe; + case 173 : itype = BPFBF_EBPFBE_INSN_JLTRBE; goto extract_sfmt_jeqrbe; + case 174 : itype = BPFBF_EBPFBE_INSN_JLT32RBE; goto extract_sfmt_jeqrbe; + case 175 : itype = BPFBF_EBPFBE_INSN_XORRBE; goto extract_sfmt_addrbe; + case 180 : itype = BPFBF_EBPFBE_INSN_MOV32IBE; goto extract_sfmt_movibe; + case 181 : itype = BPFBF_EBPFBE_INSN_JLEIBE; goto extract_sfmt_jeqibe; + case 182 : itype = BPFBF_EBPFBE_INSN_JLE32IBE; goto extract_sfmt_jeqibe; + case 183 : itype = BPFBF_EBPFBE_INSN_MOVIBE; goto extract_sfmt_movibe; + case 188 : itype = BPFBF_EBPFBE_INSN_MOV32RBE; goto extract_sfmt_movrbe; + case 189 : itype = BPFBF_EBPFBE_INSN_JLERBE; goto extract_sfmt_jeqrbe; + case 190 : itype = BPFBF_EBPFBE_INSN_JLE32RBE; goto extract_sfmt_jeqrbe; + case 191 : itype = BPFBF_EBPFBE_INSN_MOVRBE; goto extract_sfmt_movrbe; + case 195 : itype = BPFBF_EBPFBE_INSN_XADDWBE; goto extract_sfmt_xaddwbe; + case 196 : itype = BPFBF_EBPFBE_INSN_ARSH32IBE; goto extract_sfmt_addibe; + case 197 : itype = BPFBF_EBPFBE_INSN_JSLTIBE; goto extract_sfmt_jeqibe; + case 198 : itype = BPFBF_EBPFBE_INSN_JSLT32IBE; goto extract_sfmt_jeqibe; + case 199 : itype = BPFBF_EBPFBE_INSN_ARSHIBE; goto extract_sfmt_addibe; + case 204 : itype = BPFBF_EBPFBE_INSN_ARSH32RBE; goto extract_sfmt_addrbe; + case 205 : itype = BPFBF_EBPFBE_INSN_JSLTRBE; goto extract_sfmt_jeqrbe; + case 206 : itype = BPFBF_EBPFBE_INSN_JSLT32RBE; goto extract_sfmt_jeqrbe; + case 207 : itype = BPFBF_EBPFBE_INSN_ARSHRBE; goto extract_sfmt_addrbe; + case 212 : itype = BPFBF_EBPFBE_INSN_ENDLEBE; goto extract_sfmt_endlebe; + case 213 : itype = BPFBF_EBPFBE_INSN_JSLEIBE; goto extract_sfmt_jeqibe; + case 214 : itype = BPFBF_EBPFBE_INSN_JSLE32IBE; goto extract_sfmt_jeqibe; + case 219 : itype = BPFBF_EBPFBE_INSN_XADDDWBE; goto extract_sfmt_xadddwbe; + case 220 : itype = BPFBF_EBPFBE_INSN_ENDBEBE; goto extract_sfmt_endlebe; + case 221 : itype = BPFBF_EBPFBE_INSN_JSLERBE; goto extract_sfmt_jeqrbe; + case 222 : itype = BPFBF_EBPFBE_INSN_JSLE32RBE; goto extract_sfmt_jeqrbe; + default : itype = BPFBF_EBPFBE_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_addibe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addibe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_addrbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + UINT f_dstbe; + UINT f_srcbe; + + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addrbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_negbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_lddwbe.f + UINT f_dstbe; + + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negbe", "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_movibe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movibe", "f_imm32 0x%x", 'x', f_imm32, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_movrbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + UINT f_dstbe; + UINT f_srcbe; + + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_srcbe) = f_srcbe; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movrbe", "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_endlebe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_endlebe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_lddwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_lddwbe.f + UINT f_imm64_c; + UINT f_imm64_b; + UINT f_imm64_a; + UINT f_dstbe; + DI f_imm64; + /* Contents of trailing part of insn. */ + UINT word_1; + UINT word_2; + + word_1 = GETIMEMUSI (current_cpu, pc + 8); + word_2 = GETIMEMUSI (current_cpu, pc + 12); + f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); + f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); + f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); +{ + f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a)))); +} + + /* Record the fields for the semantic handler. */ + FLD (f_imm64) = f_imm64; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddwbe", "f_imm64 0x%x", 'x', f_imm64, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsw: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsh: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsh", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsb: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsb", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsdw: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsdw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + UINT f_srcbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindwbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindhbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + UINT f_srcbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindhbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindbbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + UINT f_srcbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindbbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldinddwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + UINT f_srcbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldinddwbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxwbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxhbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxhbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxbbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxbbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxdwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + FLD (f_dstbe) = f_dstbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxdwbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxhbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxhbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxbbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxbbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxdwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxdwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stbbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + HI f_offset16; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sthbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + HI f_offset16; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + HI f_offset16; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stdwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + HI f_offset16; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_jeqibe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + INT f_imm32; + HI f_offset16; + UINT f_dstbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_dstbe) = f_dstbe; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqibe", "f_offset16 0x%x", 'x', f_offset16, "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jeqrbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_dstbe) = f_dstbe; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqrbe", "f_offset16 0x%x", 'x', f_offset16, "f_dstbe 0x%x", 'x', f_dstbe, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_callbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + INT f_imm32; + UINT f_srcbe; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ja: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stbbe.f + HI f_offset16; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ja", "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_exit: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_exit", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_xadddwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xadddwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_xaddwbe: + { + const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + HI f_offset16; + UINT f_dstbe; + UINT f_srcbe; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstbe) = f_dstbe; + FLD (f_offset16) = f_offset16; + FLD (f_srcbe) = f_srcbe; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xaddwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0)); + +#undef FLD + return idesc; + } + +} diff --git a/sim/bpf/decode-be.h b/sim/bpf/decode-be.h new file mode 100644 index 00000000000..431d7c605c8 --- /dev/null +++ b/sim/bpf/decode-be.h @@ -0,0 +1,94 @@ +/* Decode header for bpfbf_ebpfbe. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef BPFBF_EBPFBE_DECODE_H +#define BPFBF_EBPFBE_DECODE_H + +extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR, + CGEN_INSN_WORD, + ARGBUF *); +extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *); +extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *); +extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family bpfbf. */ +typedef enum bpfbf_ebpfbe_insn_type { + BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_CTI_CHAIN + , BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDRBE + , BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBRBE + , BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULRBE + , BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVRBE + , BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORRBE + , BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDRBE + , BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHRBE + , BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHRBE + , BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODRBE + , BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORRBE + , BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHRBE + , BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEG32BE + , BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32RBE + , BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDABSW + , BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDINDWBE + , BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDXWBE + , BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_STXWBE + , BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STBBE + , BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_INSN_JEQIBE + , BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JGTIBE + , BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGEIBE + , BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JLTIBE + , BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLEIBE + , BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JSETIBE + , BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JNEIBE + , BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JSGTIBE + , BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGEIBE + , BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSLTIBE + , BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLEIBE + , BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_CALLBE + , BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDWBE + , BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_INSN__MAX +} BPFBF_EBPFBE_INSN_TYPE; + +/* Enum declaration for semantic formats in cpu family bpfbf. */ +typedef enum bpfbf_ebpfbe_sfmt_type { + BPFBF_EBPFBE_SFMT_EMPTY, BPFBF_EBPFBE_SFMT_ADDIBE, BPFBF_EBPFBE_SFMT_ADDRBE, BPFBF_EBPFBE_SFMT_NEGBE + , BPFBF_EBPFBE_SFMT_MOVIBE, BPFBF_EBPFBE_SFMT_MOVRBE, BPFBF_EBPFBE_SFMT_ENDLEBE, BPFBF_EBPFBE_SFMT_LDDWBE + , BPFBF_EBPFBE_SFMT_LDABSW, BPFBF_EBPFBE_SFMT_LDABSH, BPFBF_EBPFBE_SFMT_LDABSB, BPFBF_EBPFBE_SFMT_LDABSDW + , BPFBF_EBPFBE_SFMT_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDDWBE + , BPFBF_EBPFBE_SFMT_LDXWBE, BPFBF_EBPFBE_SFMT_LDXHBE, BPFBF_EBPFBE_SFMT_LDXBBE, BPFBF_EBPFBE_SFMT_LDXDWBE + , BPFBF_EBPFBE_SFMT_STXWBE, BPFBF_EBPFBE_SFMT_STXHBE, BPFBF_EBPFBE_SFMT_STXBBE, BPFBF_EBPFBE_SFMT_STXDWBE + , BPFBF_EBPFBE_SFMT_STBBE, BPFBF_EBPFBE_SFMT_STHBE, BPFBF_EBPFBE_SFMT_STWBE, BPFBF_EBPFBE_SFMT_STDWBE + , BPFBF_EBPFBE_SFMT_JEQIBE, BPFBF_EBPFBE_SFMT_JEQRBE, BPFBF_EBPFBE_SFMT_CALLBE, BPFBF_EBPFBE_SFMT_JA + , BPFBF_EBPFBE_SFMT_EXIT, BPFBF_EBPFBE_SFMT_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDWBE +} BPFBF_EBPFBE_SFMT_TYPE; + +/* Function unit handlers (user written). */ + +extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* BPFBF_EBPFBE_DECODE_H */ diff --git a/sim/bpf/decode-le.c b/sim/bpf/decode-le.c new file mode 100644 index 00000000000..8181485e4c7 --- /dev/null +++ b/sim/bpf/decode-le.c @@ -0,0 +1,1129 @@ +/* Simulator instruction decoder for bpfbf_ebpfle. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#define WANT_CPU bpfbf +#define WANT_CPU_BPFBF + +#include "sim-main.h" +#include "sim-assert.h" + +/* The instruction descriptor array. + This is computed at runtime. Space for it is not malloc'd to save a + teensy bit of cpu in the decoder. Moving it to malloc space is trivial + but won't be done until necessary (we don't currently support the runtime + addition of instructions nor an SMP machine with different cpus). */ +static IDESC bpfbf_ebpfle_insn_data[BPFBF_EBPFLE_INSN__MAX]; + +/* Commas between elements are contained in the macros. + Some of these are conditionally compiled out. */ + +static const struct insn_sem bpfbf_ebpfle_insn_sem[] = +{ + { VIRTUAL_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CTI_CHAIN, BPFBF_EBPFLE_INSN_X_CTI_CHAIN, BPFBF_EBPFLE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_SFMT_EMPTY }, + { VIRTUAL_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_SFMT_EMPTY }, + { BPF_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ADDRLE, BPFBF_EBPFLE_INSN_ADDRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_SUBRLE, BPFBF_EBPFLE_INSN_SUBRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_MULILE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_MULRLE, BPFBF_EBPFLE_INSN_MULRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_DIVRLE, BPFBF_EBPFLE_INSN_DIVRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_ORILE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ORRLE, BPFBF_EBPFLE_INSN_ORRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_OR32RLE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ANDRLE, BPFBF_EBPFLE_INSN_ANDRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_AND32RLE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_LSHRLE, BPFBF_EBPFLE_INSN_LSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_RSHRLE, BPFBF_EBPFLE_INSN_RSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_MODILE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_MODRLE, BPFBF_EBPFLE_INSN_MODRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_XORILE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_XORRLE, BPFBF_EBPFLE_INSN_XORRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ARSHRLE, BPFBF_EBPFLE_INSN_ARSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE }, + { BPF_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE }, + { BPF_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_SFMT_NEGLE }, + { BPF_INSN_NEG32LE, BPFBF_EBPFLE_INSN_NEG32LE, BPFBF_EBPFLE_SFMT_NEGLE }, + { BPF_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_SFMT_MOVILE }, + { BPF_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_SFMT_MOVRLE }, + { BPF_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_SFMT_MOVILE }, + { BPF_INSN_MOV32RLE, BPFBF_EBPFLE_INSN_MOV32RLE, BPFBF_EBPFLE_SFMT_MOVRLE }, + { BPF_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_SFMT_ENDLELE }, + { BPF_INSN_ENDBELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_SFMT_ENDLELE }, + { BPF_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_SFMT_LDDWLE }, + { BPF_INSN_LDABSW, BPFBF_EBPFLE_INSN_LDABSW, BPFBF_EBPFLE_SFMT_LDABSW }, + { BPF_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_SFMT_LDABSH }, + { BPF_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_SFMT_LDABSB }, + { BPF_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_SFMT_LDABSDW }, + { BPF_INSN_LDINDWLE, BPFBF_EBPFLE_INSN_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDWLE }, + { BPF_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDHLE }, + { BPF_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDBLE }, + { BPF_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_SFMT_LDINDDWLE }, + { BPF_INSN_LDXWLE, BPFBF_EBPFLE_INSN_LDXWLE, BPFBF_EBPFLE_SFMT_LDXWLE }, + { BPF_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_SFMT_LDXHLE }, + { BPF_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_SFMT_LDXBLE }, + { BPF_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_SFMT_LDXDWLE }, + { BPF_INSN_STXWLE, BPFBF_EBPFLE_INSN_STXWLE, BPFBF_EBPFLE_SFMT_STXWLE }, + { BPF_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_SFMT_STXHLE }, + { BPF_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_SFMT_STXBLE }, + { BPF_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_SFMT_STXDWLE }, + { BPF_INSN_STBLE, BPFBF_EBPFLE_INSN_STBLE, BPFBF_EBPFLE_SFMT_STBLE }, + { BPF_INSN_STHLE, BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_SFMT_STHLE }, + { BPF_INSN_STWLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_SFMT_STWLE }, + { BPF_INSN_STDWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_SFMT_STDWLE }, + { BPF_INSN_JEQILE, BPFBF_EBPFLE_INSN_JEQILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JGTILE, BPFBF_EBPFLE_INSN_JGTILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JGEILE, BPFBF_EBPFLE_INSN_JGEILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JLTILE, BPFBF_EBPFLE_INSN_JLTILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JLEILE, BPFBF_EBPFLE_INSN_JLEILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSETILE, BPFBF_EBPFLE_INSN_JSETILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JNEILE, BPFBF_EBPFLE_INSN_JNEILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSGTILE, BPFBF_EBPFLE_INSN_JSGTILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSGEILE, BPFBF_EBPFLE_INSN_JSGEILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSLTILE, BPFBF_EBPFLE_INSN_JSLTILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSLEILE, BPFBF_EBPFLE_INSN_JSLEILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_SFMT_JEQILE }, + { BPF_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE }, + { BPF_INSN_CALLLE, BPFBF_EBPFLE_INSN_CALLLE, BPFBF_EBPFLE_SFMT_CALLLE }, + { BPF_INSN_JA, BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_SFMT_JA }, + { BPF_INSN_EXIT, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_SFMT_EXIT }, + { BPF_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDDWLE }, + { BPF_INSN_XADDWLE, BPFBF_EBPFLE_INSN_XADDWLE, BPFBF_EBPFLE_SFMT_XADDWLE }, + { BPF_INSN_BRKPT, BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_SFMT_EXIT }, +}; + +static const struct insn_sem bpfbf_ebpfle_insn_sem_invalid = +{ + VIRTUAL_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_SFMT_EMPTY +}; + +/* Initialize an IDESC from the compile-time computable parts. */ + +static INLINE void +init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t) +{ + const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries; + + id->num = t->index; + id->sfmt = t->sfmt; + if ((int) t->type <= 0) + id->idata = & cgen_virtual_insn_table[- (int) t->type]; + else + id->idata = & insn_table[t->type]; + id->attrs = CGEN_INSN_ATTRS (id->idata); + /* Oh my god, a magic number. */ + id->length = CGEN_INSN_BITSIZE (id->idata) / 8; + +#if WITH_PROFILE_MODEL_P + id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index]; + { + SIM_DESC sd = CPU_STATE (cpu); + SIM_ASSERT (t->index == id->timing->num); + } +#endif + + /* Semantic pointers are initialized elsewhere. */ +} + +/* Initialize the instruction descriptor table. */ + +void +bpfbf_ebpfle_init_idesc_table (SIM_CPU *cpu) +{ + IDESC *id,*tabend; + const struct insn_sem *t,*tend; + int tabsize = BPFBF_EBPFLE_INSN__MAX; + IDESC *table = bpfbf_ebpfle_insn_data; + + memset (table, 0, tabsize * sizeof (IDESC)); + + /* First set all entries to the `invalid insn'. */ + t = & bpfbf_ebpfle_insn_sem_invalid; + for (id = table, tabend = table + tabsize; id < tabend; ++id) + init_idesc (cpu, id, t); + + /* Now fill in the values for the chosen cpu. */ + for (t = bpfbf_ebpfle_insn_sem, tend = t + sizeof (bpfbf_ebpfle_insn_sem) / sizeof (*t); + t != tend; ++t) + { + init_idesc (cpu, & table[t->index], t); + } + + /* Link the IDESC table into the cpu. */ + CPU_IDESC (cpu) = table; +} + +/* Given an instruction, return a pointer to its IDESC entry. */ + +const IDESC * +bpfbf_ebpfle_decode (SIM_CPU *current_cpu, IADDR pc, + CGEN_INSN_WORD base_insn, + ARGBUF *abuf) +{ + /* Result of decoder. */ + BPFBF_EBPFLE_INSN_TYPE itype; + + { + CGEN_INSN_WORD insn = base_insn; + + { + unsigned int val = (((insn >> 0) & (255 << 0))); + switch (val) + { + case 4 : itype = BPFBF_EBPFLE_INSN_ADD32ILE; goto extract_sfmt_addile; + case 5 : itype = BPFBF_EBPFLE_INSN_JA; goto extract_sfmt_ja; + case 7 : itype = BPFBF_EBPFLE_INSN_ADDILE; goto extract_sfmt_addile; + case 12 : itype = BPFBF_EBPFLE_INSN_ADD32RLE; goto extract_sfmt_addrle; + case 15 : itype = BPFBF_EBPFLE_INSN_ADDRLE; goto extract_sfmt_addrle; + case 20 : itype = BPFBF_EBPFLE_INSN_SUB32ILE; goto extract_sfmt_addile; + case 21 : itype = BPFBF_EBPFLE_INSN_JEQILE; goto extract_sfmt_jeqile; + case 22 : itype = BPFBF_EBPFLE_INSN_JEQ32ILE; goto extract_sfmt_jeqile; + case 23 : itype = BPFBF_EBPFLE_INSN_SUBILE; goto extract_sfmt_addile; + case 24 : itype = BPFBF_EBPFLE_INSN_LDDWLE; goto extract_sfmt_lddwle; + case 28 : itype = BPFBF_EBPFLE_INSN_SUB32RLE; goto extract_sfmt_addrle; + case 29 : itype = BPFBF_EBPFLE_INSN_JEQRLE; goto extract_sfmt_jeqrle; + case 30 : itype = BPFBF_EBPFLE_INSN_JEQ32RLE; goto extract_sfmt_jeqrle; + case 31 : itype = BPFBF_EBPFLE_INSN_SUBRLE; goto extract_sfmt_addrle; + case 32 : itype = BPFBF_EBPFLE_INSN_LDABSW; goto extract_sfmt_ldabsw; + case 36 : itype = BPFBF_EBPFLE_INSN_MUL32ILE; goto extract_sfmt_addile; + case 37 : itype = BPFBF_EBPFLE_INSN_JGTILE; goto extract_sfmt_jeqile; + case 38 : itype = BPFBF_EBPFLE_INSN_JGT32ILE; goto extract_sfmt_jeqile; + case 39 : itype = BPFBF_EBPFLE_INSN_MULILE; goto extract_sfmt_addile; + case 40 : itype = BPFBF_EBPFLE_INSN_LDABSH; goto extract_sfmt_ldabsh; + case 44 : itype = BPFBF_EBPFLE_INSN_MUL32RLE; goto extract_sfmt_addrle; + case 45 : itype = BPFBF_EBPFLE_INSN_JGTRLE; goto extract_sfmt_jeqrle; + case 46 : itype = BPFBF_EBPFLE_INSN_JGT32RLE; goto extract_sfmt_jeqrle; + case 47 : itype = BPFBF_EBPFLE_INSN_MULRLE; goto extract_sfmt_addrle; + case 48 : itype = BPFBF_EBPFLE_INSN_LDABSB; goto extract_sfmt_ldabsb; + case 52 : itype = BPFBF_EBPFLE_INSN_DIV32ILE; goto extract_sfmt_addile; + case 53 : itype = BPFBF_EBPFLE_INSN_JGEILE; goto extract_sfmt_jeqile; + case 54 : itype = BPFBF_EBPFLE_INSN_JGE32ILE; goto extract_sfmt_jeqile; + case 55 : itype = BPFBF_EBPFLE_INSN_DIVILE; goto extract_sfmt_addile; + case 56 : itype = BPFBF_EBPFLE_INSN_LDABSDW; goto extract_sfmt_ldabsdw; + case 60 : itype = BPFBF_EBPFLE_INSN_DIV32RLE; goto extract_sfmt_addrle; + case 61 : itype = BPFBF_EBPFLE_INSN_JGERLE; goto extract_sfmt_jeqrle; + case 62 : itype = BPFBF_EBPFLE_INSN_JGE32RLE; goto extract_sfmt_jeqrle; + case 63 : itype = BPFBF_EBPFLE_INSN_DIVRLE; goto extract_sfmt_addrle; + case 64 : itype = BPFBF_EBPFLE_INSN_LDINDWLE; goto extract_sfmt_ldindwle; + case 68 : itype = BPFBF_EBPFLE_INSN_OR32ILE; goto extract_sfmt_addile; + case 69 : itype = BPFBF_EBPFLE_INSN_JSETILE; goto extract_sfmt_jeqile; + case 70 : itype = BPFBF_EBPFLE_INSN_JSET32ILE; goto extract_sfmt_jeqile; + case 71 : itype = BPFBF_EBPFLE_INSN_ORILE; goto extract_sfmt_addile; + case 72 : itype = BPFBF_EBPFLE_INSN_LDINDHLE; goto extract_sfmt_ldindhle; + case 76 : itype = BPFBF_EBPFLE_INSN_OR32RLE; goto extract_sfmt_addrle; + case 77 : itype = BPFBF_EBPFLE_INSN_JSETRLE; goto extract_sfmt_jeqrle; + case 78 : itype = BPFBF_EBPFLE_INSN_JSET32RLE; goto extract_sfmt_jeqrle; + case 79 : itype = BPFBF_EBPFLE_INSN_ORRLE; goto extract_sfmt_addrle; + case 80 : itype = BPFBF_EBPFLE_INSN_LDINDBLE; goto extract_sfmt_ldindble; + case 84 : itype = BPFBF_EBPFLE_INSN_AND32ILE; goto extract_sfmt_addile; + case 85 : itype = BPFBF_EBPFLE_INSN_JNEILE; goto extract_sfmt_jeqile; + case 86 : itype = BPFBF_EBPFLE_INSN_JNE32ILE; goto extract_sfmt_jeqile; + case 87 : itype = BPFBF_EBPFLE_INSN_ANDILE; goto extract_sfmt_addile; + case 88 : itype = BPFBF_EBPFLE_INSN_LDINDDWLE; goto extract_sfmt_ldinddwle; + case 92 : itype = BPFBF_EBPFLE_INSN_AND32RLE; goto extract_sfmt_addrle; + case 93 : itype = BPFBF_EBPFLE_INSN_JNERLE; goto extract_sfmt_jeqrle; + case 94 : itype = BPFBF_EBPFLE_INSN_JNE32RLE; goto extract_sfmt_jeqrle; + case 95 : itype = BPFBF_EBPFLE_INSN_ANDRLE; goto extract_sfmt_addrle; + case 97 : itype = BPFBF_EBPFLE_INSN_LDXWLE; goto extract_sfmt_ldxwle; + case 98 : itype = BPFBF_EBPFLE_INSN_STWLE; goto extract_sfmt_stwle; + case 99 : itype = BPFBF_EBPFLE_INSN_STXWLE; goto extract_sfmt_stxwle; + case 100 : itype = BPFBF_EBPFLE_INSN_LSH32ILE; goto extract_sfmt_addile; + case 101 : itype = BPFBF_EBPFLE_INSN_JSGTILE; goto extract_sfmt_jeqile; + case 102 : itype = BPFBF_EBPFLE_INSN_JSGT32ILE; goto extract_sfmt_jeqile; + case 103 : itype = BPFBF_EBPFLE_INSN_LSHILE; goto extract_sfmt_addile; + case 105 : itype = BPFBF_EBPFLE_INSN_LDXHLE; goto extract_sfmt_ldxhle; + case 106 : itype = BPFBF_EBPFLE_INSN_STHLE; goto extract_sfmt_sthle; + case 107 : itype = BPFBF_EBPFLE_INSN_STXHLE; goto extract_sfmt_stxhle; + case 108 : itype = BPFBF_EBPFLE_INSN_LSH32RLE; goto extract_sfmt_addrle; + case 109 : itype = BPFBF_EBPFLE_INSN_JSGTRLE; goto extract_sfmt_jeqrle; + case 110 : itype = BPFBF_EBPFLE_INSN_JSGT32RLE; goto extract_sfmt_jeqrle; + case 111 : itype = BPFBF_EBPFLE_INSN_LSHRLE; goto extract_sfmt_addrle; + case 113 : itype = BPFBF_EBPFLE_INSN_LDXBLE; goto extract_sfmt_ldxble; + case 114 : itype = BPFBF_EBPFLE_INSN_STBLE; goto extract_sfmt_stble; + case 115 : itype = BPFBF_EBPFLE_INSN_STXBLE; goto extract_sfmt_stxble; + case 116 : itype = BPFBF_EBPFLE_INSN_RSH32ILE; goto extract_sfmt_addile; + case 117 : itype = BPFBF_EBPFLE_INSN_JSGEILE; goto extract_sfmt_jeqile; + case 118 : itype = BPFBF_EBPFLE_INSN_JSGE32ILE; goto extract_sfmt_jeqile; + case 119 : itype = BPFBF_EBPFLE_INSN_RSHILE; goto extract_sfmt_addile; + case 121 : itype = BPFBF_EBPFLE_INSN_LDXDWLE; goto extract_sfmt_ldxdwle; + case 122 : itype = BPFBF_EBPFLE_INSN_STDWLE; goto extract_sfmt_stdwle; + case 123 : itype = BPFBF_EBPFLE_INSN_STXDWLE; goto extract_sfmt_stxdwle; + case 124 : itype = BPFBF_EBPFLE_INSN_RSH32RLE; goto extract_sfmt_addrle; + case 125 : itype = BPFBF_EBPFLE_INSN_JSGERLE; goto extract_sfmt_jeqrle; + case 126 : itype = BPFBF_EBPFLE_INSN_JSGE32RLE; goto extract_sfmt_jeqrle; + case 127 : itype = BPFBF_EBPFLE_INSN_RSHRLE; goto extract_sfmt_addrle; + case 132 : itype = BPFBF_EBPFLE_INSN_NEG32LE; goto extract_sfmt_negle; + case 133 : itype = BPFBF_EBPFLE_INSN_CALLLE; goto extract_sfmt_callle; + case 135 : itype = BPFBF_EBPFLE_INSN_NEGLE; goto extract_sfmt_negle; + case 140 : itype = BPFBF_EBPFLE_INSN_BRKPT; goto extract_sfmt_exit; + case 148 : itype = BPFBF_EBPFLE_INSN_MOD32ILE; goto extract_sfmt_addile; + case 149 : itype = BPFBF_EBPFLE_INSN_EXIT; goto extract_sfmt_exit; + case 151 : itype = BPFBF_EBPFLE_INSN_MODILE; goto extract_sfmt_addile; + case 156 : itype = BPFBF_EBPFLE_INSN_MOD32RLE; goto extract_sfmt_addrle; + case 159 : itype = BPFBF_EBPFLE_INSN_MODRLE; goto extract_sfmt_addrle; + case 164 : itype = BPFBF_EBPFLE_INSN_XOR32ILE; goto extract_sfmt_addile; + case 165 : itype = BPFBF_EBPFLE_INSN_JLTILE; goto extract_sfmt_jeqile; + case 166 : itype = BPFBF_EBPFLE_INSN_JLT32ILE; goto extract_sfmt_jeqile; + case 167 : itype = BPFBF_EBPFLE_INSN_XORILE; goto extract_sfmt_addile; + case 172 : itype = BPFBF_EBPFLE_INSN_XOR32RLE; goto extract_sfmt_addrle; + case 173 : itype = BPFBF_EBPFLE_INSN_JLTRLE; goto extract_sfmt_jeqrle; + case 174 : itype = BPFBF_EBPFLE_INSN_JLT32RLE; goto extract_sfmt_jeqrle; + case 175 : itype = BPFBF_EBPFLE_INSN_XORRLE; goto extract_sfmt_addrle; + case 180 : itype = BPFBF_EBPFLE_INSN_MOV32ILE; goto extract_sfmt_movile; + case 181 : itype = BPFBF_EBPFLE_INSN_JLEILE; goto extract_sfmt_jeqile; + case 182 : itype = BPFBF_EBPFLE_INSN_JLE32ILE; goto extract_sfmt_jeqile; + case 183 : itype = BPFBF_EBPFLE_INSN_MOVILE; goto extract_sfmt_movile; + case 188 : itype = BPFBF_EBPFLE_INSN_MOV32RLE; goto extract_sfmt_movrle; + case 189 : itype = BPFBF_EBPFLE_INSN_JLERLE; goto extract_sfmt_jeqrle; + case 190 : itype = BPFBF_EBPFLE_INSN_JLE32RLE; goto extract_sfmt_jeqrle; + case 191 : itype = BPFBF_EBPFLE_INSN_MOVRLE; goto extract_sfmt_movrle; + case 195 : itype = BPFBF_EBPFLE_INSN_XADDWLE; goto extract_sfmt_xaddwle; + case 196 : itype = BPFBF_EBPFLE_INSN_ARSH32ILE; goto extract_sfmt_addile; + case 197 : itype = BPFBF_EBPFLE_INSN_JSLTILE; goto extract_sfmt_jeqile; + case 198 : itype = BPFBF_EBPFLE_INSN_JSLT32ILE; goto extract_sfmt_jeqile; + case 199 : itype = BPFBF_EBPFLE_INSN_ARSHILE; goto extract_sfmt_addile; + case 204 : itype = BPFBF_EBPFLE_INSN_ARSH32RLE; goto extract_sfmt_addrle; + case 205 : itype = BPFBF_EBPFLE_INSN_JSLTRLE; goto extract_sfmt_jeqrle; + case 206 : itype = BPFBF_EBPFLE_INSN_JSLT32RLE; goto extract_sfmt_jeqrle; + case 207 : itype = BPFBF_EBPFLE_INSN_ARSHRLE; goto extract_sfmt_addrle; + case 212 : itype = BPFBF_EBPFLE_INSN_ENDLELE; goto extract_sfmt_endlele; + case 213 : itype = BPFBF_EBPFLE_INSN_JSLEILE; goto extract_sfmt_jeqile; + case 214 : itype = BPFBF_EBPFLE_INSN_JSLE32ILE; goto extract_sfmt_jeqile; + case 219 : itype = BPFBF_EBPFLE_INSN_XADDDWLE; goto extract_sfmt_xadddwle; + case 220 : itype = BPFBF_EBPFLE_INSN_ENDBELE; goto extract_sfmt_endlele; + case 221 : itype = BPFBF_EBPFLE_INSN_JSLERLE; goto extract_sfmt_jeqrle; + case 222 : itype = BPFBF_EBPFLE_INSN_JSLE32RLE; goto extract_sfmt_jeqrle; + default : itype = BPFBF_EBPFLE_INSN_X_INVALID; goto extract_sfmt_empty; + } + } + } + + /* The instruction has been decoded, now extract the fields. */ + + extract_sfmt_empty: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_addile: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addile", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_addrle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + UINT f_srcle; + UINT f_dstle; + + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addrle", "f_dstle 0x%x", 'x', f_dstle, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_negle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_lddwle.f + UINT f_dstle; + + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negle", "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_movile: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movile", "f_imm32 0x%x", 'x', f_imm32, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_movrle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + UINT f_srcle; + UINT f_dstle; + + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_srcle) = f_srcle; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movrle", "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_endlele: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_endlele", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_lddwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_lddwle.f + UINT f_imm64_c; + UINT f_imm64_b; + UINT f_imm64_a; + UINT f_dstle; + DI f_imm64; + /* Contents of trailing part of insn. */ + UINT word_1; + UINT word_2; + + word_1 = GETIMEMUSI (current_cpu, pc + 8); + word_2 = GETIMEMUSI (current_cpu, pc + 12); + f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); + f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); + f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); +{ + f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a)))); +} + + /* Record the fields for the semantic handler. */ + FLD (f_imm64) = f_imm64; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddwle", "f_imm64 0x%x", 'x', f_imm64, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsw: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsh: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsh", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsb: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsb", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldabsdw: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsdw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + UINT f_srcle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindwle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindhle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + UINT f_srcle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindhle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldindble: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + UINT f_srcle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindble", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldinddwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + UINT f_srcle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldinddwle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxwle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxhle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxhle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxble: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxble", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ldxdwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + FLD (f_dstle) = f_dstle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxdwle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxhle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxhle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxble: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxble", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stxdwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxdwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stble: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + HI f_offset16; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stble", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_sthle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + HI f_offset16; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + HI f_offset16; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stwle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_stdwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + HI f_offset16; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdwle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_jeqile: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + INT f_imm32; + HI f_offset16; + UINT f_dstle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_dstle) = f_dstle; + FLD (f_imm32) = f_imm32; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqile", "f_offset16 0x%x", 'x', f_offset16, "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_jeqrle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + FLD (f_dstle) = f_dstle; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqrle", "f_offset16 0x%x", 'x', f_offset16, "f_dstle 0x%x", 'x', f_dstle, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_callle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldindwle.f + INT f_imm32; + UINT f_srcle; + + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_imm32) = f_imm32; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_ja: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_stble.f + HI f_offset16; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_offset16) = f_offset16; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ja", "f_offset16 0x%x", 'x', f_offset16, (char *) 0)); + +#if WITH_PROFILE_MODEL_P + /* Record the fields for profiling. */ + if (PROFILE_MODEL_P (current_cpu)) + { + } +#endif +#undef FLD + return idesc; + } + + extract_sfmt_exit: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; +#define FLD(f) abuf->fields.sfmt_empty.f + + + /* Record the fields for the semantic handler. */ + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_exit", (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_xadddwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xadddwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + + extract_sfmt_xaddwle: + { + const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype]; + CGEN_INSN_WORD insn = base_insn; +#define FLD(f) abuf->fields.sfmt_ldxwle.f + HI f_offset16; + UINT f_srcle; + UINT f_dstle; + + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); + + /* Record the fields for the semantic handler. */ + FLD (f_dstle) = f_dstle; + FLD (f_offset16) = f_offset16; + FLD (f_srcle) = f_srcle; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xaddwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0)); + +#undef FLD + return idesc; + } + +} diff --git a/sim/bpf/decode-le.h b/sim/bpf/decode-le.h new file mode 100644 index 00000000000..d854f1d4ed0 --- /dev/null +++ b/sim/bpf/decode-le.h @@ -0,0 +1,94 @@ +/* Decode header for bpfbf_ebpfle. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef BPFBF_EBPFLE_DECODE_H +#define BPFBF_EBPFLE_DECODE_H + +extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR, + CGEN_INSN_WORD, + ARGBUF *); +extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *); +extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *); +extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *); + +/* Enum declaration for instructions in cpu family bpfbf. */ +typedef enum bpfbf_ebpfle_insn_type { + BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_CTI_CHAIN + , BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDRLE + , BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBRLE + , BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_INSN_MULRLE + , BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVRLE + , BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_INSN_ORRLE + , BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDRLE + , BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHRLE + , BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHRLE + , BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_INSN_MODRLE + , BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_INSN_XORRLE + , BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHRLE + , BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEG32LE + , BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32RLE + , BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDABSW + , BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDINDWLE + , BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDXWLE + , BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_STXWLE + , BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STBLE + , BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_INSN_JEQILE + , BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JGTILE + , BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGEILE + , BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JLTILE + , BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLEILE + , BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JSETILE + , BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JNEILE + , BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JSGTILE + , BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGEILE + , BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSLTILE + , BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLEILE + , BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_CALLLE + , BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDWLE + , BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_INSN__MAX +} BPFBF_EBPFLE_INSN_TYPE; + +/* Enum declaration for semantic formats in cpu family bpfbf. */ +typedef enum bpfbf_ebpfle_sfmt_type { + BPFBF_EBPFLE_SFMT_EMPTY, BPFBF_EBPFLE_SFMT_ADDILE, BPFBF_EBPFLE_SFMT_ADDRLE, BPFBF_EBPFLE_SFMT_NEGLE + , BPFBF_EBPFLE_SFMT_MOVILE, BPFBF_EBPFLE_SFMT_MOVRLE, BPFBF_EBPFLE_SFMT_ENDLELE, BPFBF_EBPFLE_SFMT_LDDWLE + , BPFBF_EBPFLE_SFMT_LDABSW, BPFBF_EBPFLE_SFMT_LDABSH, BPFBF_EBPFLE_SFMT_LDABSB, BPFBF_EBPFLE_SFMT_LDABSDW + , BPFBF_EBPFLE_SFMT_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDDWLE + , BPFBF_EBPFLE_SFMT_LDXWLE, BPFBF_EBPFLE_SFMT_LDXHLE, BPFBF_EBPFLE_SFMT_LDXBLE, BPFBF_EBPFLE_SFMT_LDXDWLE + , BPFBF_EBPFLE_SFMT_STXWLE, BPFBF_EBPFLE_SFMT_STXHLE, BPFBF_EBPFLE_SFMT_STXBLE, BPFBF_EBPFLE_SFMT_STXDWLE + , BPFBF_EBPFLE_SFMT_STBLE, BPFBF_EBPFLE_SFMT_STHLE, BPFBF_EBPFLE_SFMT_STWLE, BPFBF_EBPFLE_SFMT_STDWLE + , BPFBF_EBPFLE_SFMT_JEQILE, BPFBF_EBPFLE_SFMT_JEQRLE, BPFBF_EBPFLE_SFMT_CALLLE, BPFBF_EBPFLE_SFMT_JA + , BPFBF_EBPFLE_SFMT_EXIT, BPFBF_EBPFLE_SFMT_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDWLE +} BPFBF_EBPFLE_SFMT_TYPE; + +/* Function unit handlers (user written). */ + +extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); + +/* Profiling before/after handlers (user written) */ + +extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/); +extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/); + +#endif /* BPFBF_EBPFLE_DECODE_H */ diff --git a/sim/bpf/defs-be.h b/sim/bpf/defs-be.h new file mode 100644 index 00000000000..fc6dbb4d7a4 --- /dev/null +++ b/sim/bpf/defs-be.h @@ -0,0 +1,383 @@ +/* ISA definitions header for ebpfbe. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef DEFS_BPFBF_EBPFBE_H +#define DEFS_BPFBF_EBPFBE_H + +/* Instruction argument buffer. */ + +union sem_fields { + struct { /* no operands */ + int empty; + } sfmt_empty; + struct { /* */ + INT f_imm32; + UINT f_srcbe; + } sfmt_ldindwbe; + struct { /* */ + DI f_imm64; + UINT f_dstbe; + } sfmt_lddwbe; + struct { /* */ + INT f_imm32; + UINT f_dstbe; + HI f_offset16; + } sfmt_stbbe; + struct { /* */ + UINT f_dstbe; + UINT f_srcbe; + HI f_offset16; + } sfmt_ldxwbe; +#if WITH_SCACHE_PBB + /* Writeback handler. */ + struct { + /* Pointer to argbuf entry for insn whose results need writing back. */ + const struct argbuf *abuf; + } write; + /* x-before handler */ + struct { + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ + int first_p; + } before; + /* x-after handler */ + struct { + int empty; + } after; + /* This entry is used to terminate each pbb. */ + struct { + /* Number of insns in pbb. */ + int insn_count; + /* Next pbb to execute. */ + SCACHE *next; + SCACHE *branch_target; + } chain; +#endif +}; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ + union sem semantic; + int written; + union sem_fields fields; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_ADDIBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ADDIBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_ADDRBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ADDRBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_NEGBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_NEGBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_ENDLEBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ENDLEBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDDWBE_VARS \ + UINT f_imm64_a; \ + UINT f_imm64_b; \ + UINT f_imm64_c; \ + DI f_imm64; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_srcbe; \ + UINT f_op_class; \ + /* Contents of trailing part of insn. */ \ + UINT word_1; \ + UINT word_2; \ + unsigned int length; +#define EXTRACT_IFMT_LDDWBE_CODE \ + length = 16; \ + word_1 = GETIMEMUSI (current_cpu, pc + 8); \ + word_2 = GETIMEMUSI (current_cpu, pc + 12); \ + f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ + f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \ +{\ + f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\ +}\ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDABSW_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDABSW_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDINDWBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_srcbe; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDINDWBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDXWBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_srcbe; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDXWBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_STBBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_srcbe; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_STBBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JEQIBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JEQIBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JEQRBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_dstbe; \ + UINT f_op_code; \ + UINT f_srcbe; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JEQRBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_CALLBE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_CALLBE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JA_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JA_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_EXIT_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_EXIT_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#endif /* DEFS_BPFBF_EBPFBE_H */ diff --git a/sim/bpf/defs-le.h b/sim/bpf/defs-le.h new file mode 100644 index 00000000000..aeb8a44e884 --- /dev/null +++ b/sim/bpf/defs-le.h @@ -0,0 +1,383 @@ +/* ISA definitions header for ebpfle. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef DEFS_BPFBF_EBPFLE_H +#define DEFS_BPFBF_EBPFLE_H + +/* Instruction argument buffer. */ + +union sem_fields { + struct { /* no operands */ + int empty; + } sfmt_empty; + struct { /* */ + INT f_imm32; + UINT f_srcle; + } sfmt_ldindwle; + struct { /* */ + DI f_imm64; + UINT f_dstle; + } sfmt_lddwle; + struct { /* */ + INT f_imm32; + UINT f_dstle; + HI f_offset16; + } sfmt_stble; + struct { /* */ + UINT f_dstle; + UINT f_srcle; + HI f_offset16; + } sfmt_ldxwle; +#if WITH_SCACHE_PBB + /* Writeback handler. */ + struct { + /* Pointer to argbuf entry for insn whose results need writing back. */ + const struct argbuf *abuf; + } write; + /* x-before handler */ + struct { + /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ + int first_p; + } before; + /* x-after handler */ + struct { + int empty; + } after; + /* This entry is used to terminate each pbb. */ + struct { + /* Number of insns in pbb. */ + int insn_count; + /* Next pbb to execute. */ + SCACHE *next; + SCACHE *branch_target; + } chain; +#endif +}; + +/* The ARGBUF struct. */ +struct argbuf { + /* These are the baseclass definitions. */ + IADDR addr; + const IDESC *idesc; + char trace_p; + char profile_p; + /* ??? Temporary hack for skip insns. */ + char skip_count; + char unused; + /* cpu specific data follows */ + union sem semantic; + int written; + union sem_fields fields; +}; + +/* A cached insn. + + ??? SCACHE used to contain more than just argbuf. We could delete the + type entirely and always just use ARGBUF, but for future concerns and as + a level of abstraction it is left in. */ + +struct scache { + struct argbuf argbuf; +}; + +/* Macros to simplify extraction, reading and semantic code. + These define and assign the local vars that contain the insn's fields. */ + +#define EXTRACT_IFMT_EMPTY_VARS \ + unsigned int length; +#define EXTRACT_IFMT_EMPTY_CODE \ + length = 0; \ + +#define EXTRACT_IFMT_ADDILE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ADDILE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_ADDRLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ADDRLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_NEGLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_NEGLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_ENDLELE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_ENDLELE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDDWLE_VARS \ + UINT f_imm64_a; \ + UINT f_imm64_b; \ + UINT f_imm64_c; \ + DI f_imm64; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_dstle; \ + UINT f_op_class; \ + /* Contents of trailing part of insn. */ \ + UINT word_1; \ + UINT word_2; \ + unsigned int length; +#define EXTRACT_IFMT_LDDWLE_CODE \ + length = 16; \ + word_1 = GETIMEMUSI (current_cpu, pc + 8); \ + word_2 = GETIMEMUSI (current_cpu, pc + 12); \ + f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ + f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \ +{\ + f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\ +}\ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDABSW_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDABSW_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDINDWLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_dstle; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDINDWLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_LDXWLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_dstle; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_LDXWLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_STBLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_mode; \ + UINT f_op_size; \ + UINT f_dstle; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_STBLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \ + f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JEQILE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JEQILE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JEQRLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_srcle; \ + UINT f_op_code; \ + UINT f_dstle; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JEQRLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_CALLLE_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_CALLLE_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_JA_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_JA_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#define EXTRACT_IFMT_EXIT_VARS \ + INT f_imm32; \ + HI f_offset16; \ + UINT f_regs; \ + UINT f_op_code; \ + UINT f_op_src; \ + UINT f_op_class; \ + unsigned int length; +#define EXTRACT_IFMT_EXIT_CODE \ + length = 8; \ + f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \ + f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \ + f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \ + f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \ + f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \ + f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \ + +#endif /* DEFS_BPFBF_EBPFLE_H */ diff --git a/sim/bpf/sem-be.c b/sim/bpf/sem-be.c new file mode 100644 index 00000000000..12b65c77a13 --- /dev/null +++ b/sim/bpf/sem-be.c @@ -0,0 +1,3207 @@ +/* Simulator instruction semantics for bpfbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#define WANT_CPU bpfbf +#define WANT_CPU_BPFBF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) + +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef CGEN_TRACE_RESULT +#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + +/* x-invalid: --invalid-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + + return vpc; +#undef FLD +} + +/* x-after: --after-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFBE + bpfbf_ebpfbe_pbb_after (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-before: --before-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFBE + bpfbf_ebpfbe_pbb_before (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-cti-chain: --cti-chain-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFBE +#ifdef DEFINE_SWITCH + vpc = bpfbf_ebpfbe_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = bpfbf_ebpfbe_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-chain: --chain-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFBE + vpc = bpfbf_ebpfbe_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-begin: --begin-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFBE +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* addibe: add $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,addibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* addrbe: add $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,addrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* add32ibe: add32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,add32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ADDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* add32rbe: add32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,add32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ADDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subibe: sub $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,subibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SUBDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* subrbe: sub $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,subrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SUBDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* sub32ibe: sub32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,sub32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SUBSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sub32rbe: sub32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,sub32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SUBSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mulibe: mul $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mulibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MULDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mulrbe: mul $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mulrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MULDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mul32ibe: mul32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mul32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MULSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mul32rbe: mul32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mul32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MULSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* divibe: div $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,divibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = DIVDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* divrbe: div $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,divrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = DIVDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* div32ibe: div32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,div32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = DIVSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* div32rbe: div32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,div32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = DIVSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* oribe: or $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,oribe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ORDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* orrbe: or $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,orrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ORDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* or32ibe: or32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,or32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ORSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* or32rbe: or32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,or32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ORSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andibe: and $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,andibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ANDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* andrbe: and $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,andrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ANDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* and32ibe: and32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,and32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ANDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* and32rbe: and32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,and32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ANDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lshibe: lsh $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,lshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SLLDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lshrbe: lsh $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,lshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SLLDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lsh32ibe: lsh32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,lsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SLLSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lsh32rbe: lsh32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,lsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SLLSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* rshibe: rsh $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,rshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRLDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* rshrbe: rsh $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,rshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRLDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* rsh32ibe: rsh32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,rsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRLSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* rsh32rbe: rsh32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,rsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRLSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* modibe: mod $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,modibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MODDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* modrbe: mod $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,modrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MODDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mod32ibe: mod32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mod32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MODSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mod32rbe: mod32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mod32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MODSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xoribe: xor $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xoribe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = XORDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* xorrbe: xor $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xorrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = XORDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* xor32ibe: xor32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xor32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = XORSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xor32rbe: xor32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xor32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = XORSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* arshibe: arsh $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,arshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRADI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* arshrbe: arsh $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,arshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRADI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* arsh32ibe: arsh32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,arsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRASI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* arsh32rbe: arsh32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,arsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRASI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* negbe: neg $dstbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,negbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = NEGDI (CPU (h_gpr[FLD (f_dstbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* neg32be: neg32 $dstbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,neg32be) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = NEGSI (CPU (h_gpr[FLD (f_dstbe)])); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movibe: mov $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,movibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = FLD (f_imm32); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* movrbe: mov $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,movrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = CPU (h_gpr[FLD (f_srcbe)]); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mov32ibe: mov32 $dstbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mov32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = FLD (f_imm32); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mov32rbe: mov32 $dstbe,$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,mov32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = CPU (h_gpr[FLD (f_srcbe)]); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* endlebe: endle $dstbe,$endsize */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,endlebe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = bpfbf_endle (current_cpu, CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* endbebe: endbe $dstbe,$endsize */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,endbebe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = bpfbf_endbe (current_cpu, CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lddwbe: lddw $dstbe,$imm64 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,lddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 16); + + { + DI opval = FLD (f_imm64); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsw: ldabsw $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsh: ldabsh $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldabsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsb: ldabsb $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldabsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsdw: ldabsdw $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldabsdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldindwbe: ldindw $srcbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldindwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldindhbe: ldindh $srcbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldindhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldindbbe: ldindb $srcbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldindbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldinddwbe: ldinddw $srcbe,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldinddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldxwbe: ldxw $dstbe,[$srcbe+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldxwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxhbe: ldxh $dstbe,[$srcbe+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldxhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxbbe: ldxb $dstbe,[$srcbe+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldxbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxdwbe: ldxdw $dstbe,[$srcbe+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ldxdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstbe)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* stxwbe: stxw [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stxwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = CPU (h_gpr[FLD (f_srcbe)]); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxhbe: stxh [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stxhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = CPU (h_gpr[FLD (f_srcbe)]); + SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxbbe: stxb [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stxbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = CPU (h_gpr[FLD (f_srcbe)]); + SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxdwbe: stxdw [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stxdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = CPU (h_gpr[FLD (f_srcbe)]); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* stbbe: stb [$dstbe+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = FLD (f_imm32); + SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sthbe: sth [$dstbe+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,sthbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = FLD (f_imm32); + SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stwbe: stw [$dstbe+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = FLD (f_imm32); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stdwbe: stdw [$dstbe+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,stdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = FLD (f_imm32); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* jeqibe: jeq $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jeqibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeqrbe: jeq $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jeqrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeq32ibe: jeq32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jeq32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeq32rbe: jeq32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jeq32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgtibe: jgt $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgtibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgtrbe: jgt $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgtrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgt32ibe: jgt32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgt32rbe: jgt32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgeibe: jge $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgeibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgerbe: jge $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jgerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jge32ibe: jge32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jge32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jge32rbe: jge32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jge32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jltibe: jlt $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jltibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jltrbe: jlt $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jltrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlt32ibe: jlt32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jlt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlt32rbe: jlt32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jlt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jleibe: jle $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jleibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlerbe: jle $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jlerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jle32ibe: jle32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jle32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jle32rbe: jle32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jle32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsetibe: jset $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsetibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsetrbe: jset $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsetrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jset32ibe: jset32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jset32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jset32rbe: jset32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jset32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jneibe: jne $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jneibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jnerbe: jne $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jnerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jne32ibe: jne32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jne32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jne32rbe: jne32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jne32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgtibe: jsgt $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgtibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgtrbe: jsgt $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgtrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgt32ibe: jsgt32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgt32rbe: jsgt32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgeibe: jsge $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgeibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgerbe: jsge $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsgerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsge32ibe: jsge32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsge32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsge32rbe: jsge32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsge32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsltibe: jslt $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsltibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsltrbe: jslt $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsltrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslt32ibe: jslt32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jslt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslt32rbe: jslt32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jslt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsleibe: jsle $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsleibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslerbe: jsle $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jslerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsle32ibe: jsle32 $dstbe,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsle32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsle32rbe: jsle32 $dstbe,$srcbe,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,jsle32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* callbe: call $disp32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,callbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_call (current_cpu, FLD (f_imm32), FLD (f_srcbe)); + + return vpc; +#undef FLD +} + +/* ja: ja $disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,ja) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stbbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* exit: exit */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,exit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_exit (current_cpu); + + return vpc; +#undef FLD +} + +/* xadddwbe: xadddw [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xadddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +{ + DI tmp_tmp; + tmp_tmp = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16))); + { + DI opval = ADDDI (tmp_tmp, CPU (h_gpr[FLD (f_srcbe)])); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } +} + + return vpc; +#undef FLD +} + +/* xaddwbe: xaddw [$dstbe+$offset16],$srcbe */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,xaddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwbe.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +{ + SI tmp_tmp; + tmp_tmp = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16))); + { + SI opval = ADDSI (tmp_tmp, CPU (h_gpr[FLD (f_srcbe)])); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* brkpt: brkpt */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfbe,brkpt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_breakpoint (current_cpu); + + return vpc; +#undef FLD +} + +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { BPFBF_EBPFBE_INSN_X_INVALID, SEM_FN_NAME (bpfbf_ebpfbe,x_invalid) }, + { BPFBF_EBPFBE_INSN_X_AFTER, SEM_FN_NAME (bpfbf_ebpfbe,x_after) }, + { BPFBF_EBPFBE_INSN_X_BEFORE, SEM_FN_NAME (bpfbf_ebpfbe,x_before) }, + { BPFBF_EBPFBE_INSN_X_CTI_CHAIN, SEM_FN_NAME (bpfbf_ebpfbe,x_cti_chain) }, + { BPFBF_EBPFBE_INSN_X_CHAIN, SEM_FN_NAME (bpfbf_ebpfbe,x_chain) }, + { BPFBF_EBPFBE_INSN_X_BEGIN, SEM_FN_NAME (bpfbf_ebpfbe,x_begin) }, + { BPFBF_EBPFBE_INSN_ADDIBE, SEM_FN_NAME (bpfbf_ebpfbe,addibe) }, + { BPFBF_EBPFBE_INSN_ADDRBE, SEM_FN_NAME (bpfbf_ebpfbe,addrbe) }, + { BPFBF_EBPFBE_INSN_ADD32IBE, SEM_FN_NAME (bpfbf_ebpfbe,add32ibe) }, + { BPFBF_EBPFBE_INSN_ADD32RBE, SEM_FN_NAME (bpfbf_ebpfbe,add32rbe) }, + { BPFBF_EBPFBE_INSN_SUBIBE, SEM_FN_NAME (bpfbf_ebpfbe,subibe) }, + { BPFBF_EBPFBE_INSN_SUBRBE, SEM_FN_NAME (bpfbf_ebpfbe,subrbe) }, + { BPFBF_EBPFBE_INSN_SUB32IBE, SEM_FN_NAME (bpfbf_ebpfbe,sub32ibe) }, + { BPFBF_EBPFBE_INSN_SUB32RBE, SEM_FN_NAME (bpfbf_ebpfbe,sub32rbe) }, + { BPFBF_EBPFBE_INSN_MULIBE, SEM_FN_NAME (bpfbf_ebpfbe,mulibe) }, + { BPFBF_EBPFBE_INSN_MULRBE, SEM_FN_NAME (bpfbf_ebpfbe,mulrbe) }, + { BPFBF_EBPFBE_INSN_MUL32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mul32ibe) }, + { BPFBF_EBPFBE_INSN_MUL32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mul32rbe) }, + { BPFBF_EBPFBE_INSN_DIVIBE, SEM_FN_NAME (bpfbf_ebpfbe,divibe) }, + { BPFBF_EBPFBE_INSN_DIVRBE, SEM_FN_NAME (bpfbf_ebpfbe,divrbe) }, + { BPFBF_EBPFBE_INSN_DIV32IBE, SEM_FN_NAME (bpfbf_ebpfbe,div32ibe) }, + { BPFBF_EBPFBE_INSN_DIV32RBE, SEM_FN_NAME (bpfbf_ebpfbe,div32rbe) }, + { BPFBF_EBPFBE_INSN_ORIBE, SEM_FN_NAME (bpfbf_ebpfbe,oribe) }, + { BPFBF_EBPFBE_INSN_ORRBE, SEM_FN_NAME (bpfbf_ebpfbe,orrbe) }, + { BPFBF_EBPFBE_INSN_OR32IBE, SEM_FN_NAME (bpfbf_ebpfbe,or32ibe) }, + { BPFBF_EBPFBE_INSN_OR32RBE, SEM_FN_NAME (bpfbf_ebpfbe,or32rbe) }, + { BPFBF_EBPFBE_INSN_ANDIBE, SEM_FN_NAME (bpfbf_ebpfbe,andibe) }, + { BPFBF_EBPFBE_INSN_ANDRBE, SEM_FN_NAME (bpfbf_ebpfbe,andrbe) }, + { BPFBF_EBPFBE_INSN_AND32IBE, SEM_FN_NAME (bpfbf_ebpfbe,and32ibe) }, + { BPFBF_EBPFBE_INSN_AND32RBE, SEM_FN_NAME (bpfbf_ebpfbe,and32rbe) }, + { BPFBF_EBPFBE_INSN_LSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,lshibe) }, + { BPFBF_EBPFBE_INSN_LSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,lshrbe) }, + { BPFBF_EBPFBE_INSN_LSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,lsh32ibe) }, + { BPFBF_EBPFBE_INSN_LSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,lsh32rbe) }, + { BPFBF_EBPFBE_INSN_RSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,rshibe) }, + { BPFBF_EBPFBE_INSN_RSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,rshrbe) }, + { BPFBF_EBPFBE_INSN_RSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,rsh32ibe) }, + { BPFBF_EBPFBE_INSN_RSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,rsh32rbe) }, + { BPFBF_EBPFBE_INSN_MODIBE, SEM_FN_NAME (bpfbf_ebpfbe,modibe) }, + { BPFBF_EBPFBE_INSN_MODRBE, SEM_FN_NAME (bpfbf_ebpfbe,modrbe) }, + { BPFBF_EBPFBE_INSN_MOD32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mod32ibe) }, + { BPFBF_EBPFBE_INSN_MOD32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mod32rbe) }, + { BPFBF_EBPFBE_INSN_XORIBE, SEM_FN_NAME (bpfbf_ebpfbe,xoribe) }, + { BPFBF_EBPFBE_INSN_XORRBE, SEM_FN_NAME (bpfbf_ebpfbe,xorrbe) }, + { BPFBF_EBPFBE_INSN_XOR32IBE, SEM_FN_NAME (bpfbf_ebpfbe,xor32ibe) }, + { BPFBF_EBPFBE_INSN_XOR32RBE, SEM_FN_NAME (bpfbf_ebpfbe,xor32rbe) }, + { BPFBF_EBPFBE_INSN_ARSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,arshibe) }, + { BPFBF_EBPFBE_INSN_ARSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,arshrbe) }, + { BPFBF_EBPFBE_INSN_ARSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,arsh32ibe) }, + { BPFBF_EBPFBE_INSN_ARSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,arsh32rbe) }, + { BPFBF_EBPFBE_INSN_NEGBE, SEM_FN_NAME (bpfbf_ebpfbe,negbe) }, + { BPFBF_EBPFBE_INSN_NEG32BE, SEM_FN_NAME (bpfbf_ebpfbe,neg32be) }, + { BPFBF_EBPFBE_INSN_MOVIBE, SEM_FN_NAME (bpfbf_ebpfbe,movibe) }, + { BPFBF_EBPFBE_INSN_MOVRBE, SEM_FN_NAME (bpfbf_ebpfbe,movrbe) }, + { BPFBF_EBPFBE_INSN_MOV32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mov32ibe) }, + { BPFBF_EBPFBE_INSN_MOV32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mov32rbe) }, + { BPFBF_EBPFBE_INSN_ENDLEBE, SEM_FN_NAME (bpfbf_ebpfbe,endlebe) }, + { BPFBF_EBPFBE_INSN_ENDBEBE, SEM_FN_NAME (bpfbf_ebpfbe,endbebe) }, + { BPFBF_EBPFBE_INSN_LDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,lddwbe) }, + { BPFBF_EBPFBE_INSN_LDABSW, SEM_FN_NAME (bpfbf_ebpfbe,ldabsw) }, + { BPFBF_EBPFBE_INSN_LDABSH, SEM_FN_NAME (bpfbf_ebpfbe,ldabsh) }, + { BPFBF_EBPFBE_INSN_LDABSB, SEM_FN_NAME (bpfbf_ebpfbe,ldabsb) }, + { BPFBF_EBPFBE_INSN_LDABSDW, SEM_FN_NAME (bpfbf_ebpfbe,ldabsdw) }, + { BPFBF_EBPFBE_INSN_LDINDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindwbe) }, + { BPFBF_EBPFBE_INSN_LDINDHBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindhbe) }, + { BPFBF_EBPFBE_INSN_LDINDBBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindbbe) }, + { BPFBF_EBPFBE_INSN_LDINDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldinddwbe) }, + { BPFBF_EBPFBE_INSN_LDXWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxwbe) }, + { BPFBF_EBPFBE_INSN_LDXHBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxhbe) }, + { BPFBF_EBPFBE_INSN_LDXBBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxbbe) }, + { BPFBF_EBPFBE_INSN_LDXDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxdwbe) }, + { BPFBF_EBPFBE_INSN_STXWBE, SEM_FN_NAME (bpfbf_ebpfbe,stxwbe) }, + { BPFBF_EBPFBE_INSN_STXHBE, SEM_FN_NAME (bpfbf_ebpfbe,stxhbe) }, + { BPFBF_EBPFBE_INSN_STXBBE, SEM_FN_NAME (bpfbf_ebpfbe,stxbbe) }, + { BPFBF_EBPFBE_INSN_STXDWBE, SEM_FN_NAME (bpfbf_ebpfbe,stxdwbe) }, + { BPFBF_EBPFBE_INSN_STBBE, SEM_FN_NAME (bpfbf_ebpfbe,stbbe) }, + { BPFBF_EBPFBE_INSN_STHBE, SEM_FN_NAME (bpfbf_ebpfbe,sthbe) }, + { BPFBF_EBPFBE_INSN_STWBE, SEM_FN_NAME (bpfbf_ebpfbe,stwbe) }, + { BPFBF_EBPFBE_INSN_STDWBE, SEM_FN_NAME (bpfbf_ebpfbe,stdwbe) }, + { BPFBF_EBPFBE_INSN_JEQIBE, SEM_FN_NAME (bpfbf_ebpfbe,jeqibe) }, + { BPFBF_EBPFBE_INSN_JEQRBE, SEM_FN_NAME (bpfbf_ebpfbe,jeqrbe) }, + { BPFBF_EBPFBE_INSN_JEQ32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jeq32ibe) }, + { BPFBF_EBPFBE_INSN_JEQ32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jeq32rbe) }, + { BPFBF_EBPFBE_INSN_JGTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jgtibe) }, + { BPFBF_EBPFBE_INSN_JGTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jgtrbe) }, + { BPFBF_EBPFBE_INSN_JGT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jgt32ibe) }, + { BPFBF_EBPFBE_INSN_JGT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jgt32rbe) }, + { BPFBF_EBPFBE_INSN_JGEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jgeibe) }, + { BPFBF_EBPFBE_INSN_JGERBE, SEM_FN_NAME (bpfbf_ebpfbe,jgerbe) }, + { BPFBF_EBPFBE_INSN_JGE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jge32ibe) }, + { BPFBF_EBPFBE_INSN_JGE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jge32rbe) }, + { BPFBF_EBPFBE_INSN_JLTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jltibe) }, + { BPFBF_EBPFBE_INSN_JLTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jltrbe) }, + { BPFBF_EBPFBE_INSN_JLT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jlt32ibe) }, + { BPFBF_EBPFBE_INSN_JLT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jlt32rbe) }, + { BPFBF_EBPFBE_INSN_JLEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jleibe) }, + { BPFBF_EBPFBE_INSN_JLERBE, SEM_FN_NAME (bpfbf_ebpfbe,jlerbe) }, + { BPFBF_EBPFBE_INSN_JLE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jle32ibe) }, + { BPFBF_EBPFBE_INSN_JLE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jle32rbe) }, + { BPFBF_EBPFBE_INSN_JSETIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsetibe) }, + { BPFBF_EBPFBE_INSN_JSETRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsetrbe) }, + { BPFBF_EBPFBE_INSN_JSET32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jset32ibe) }, + { BPFBF_EBPFBE_INSN_JSET32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jset32rbe) }, + { BPFBF_EBPFBE_INSN_JNEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jneibe) }, + { BPFBF_EBPFBE_INSN_JNERBE, SEM_FN_NAME (bpfbf_ebpfbe,jnerbe) }, + { BPFBF_EBPFBE_INSN_JNE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jne32ibe) }, + { BPFBF_EBPFBE_INSN_JNE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jne32rbe) }, + { BPFBF_EBPFBE_INSN_JSGTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgtibe) }, + { BPFBF_EBPFBE_INSN_JSGTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgtrbe) }, + { BPFBF_EBPFBE_INSN_JSGT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgt32ibe) }, + { BPFBF_EBPFBE_INSN_JSGT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgt32rbe) }, + { BPFBF_EBPFBE_INSN_JSGEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgeibe) }, + { BPFBF_EBPFBE_INSN_JSGERBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgerbe) }, + { BPFBF_EBPFBE_INSN_JSGE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsge32ibe) }, + { BPFBF_EBPFBE_INSN_JSGE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsge32rbe) }, + { BPFBF_EBPFBE_INSN_JSLTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsltibe) }, + { BPFBF_EBPFBE_INSN_JSLTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsltrbe) }, + { BPFBF_EBPFBE_INSN_JSLT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jslt32ibe) }, + { BPFBF_EBPFBE_INSN_JSLT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jslt32rbe) }, + { BPFBF_EBPFBE_INSN_JSLEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsleibe) }, + { BPFBF_EBPFBE_INSN_JSLERBE, SEM_FN_NAME (bpfbf_ebpfbe,jslerbe) }, + { BPFBF_EBPFBE_INSN_JSLE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsle32ibe) }, + { BPFBF_EBPFBE_INSN_JSLE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsle32rbe) }, + { BPFBF_EBPFBE_INSN_CALLBE, SEM_FN_NAME (bpfbf_ebpfbe,callbe) }, + { BPFBF_EBPFBE_INSN_JA, SEM_FN_NAME (bpfbf_ebpfbe,ja) }, + { BPFBF_EBPFBE_INSN_EXIT, SEM_FN_NAME (bpfbf_ebpfbe,exit) }, + { BPFBF_EBPFBE_INSN_XADDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,xadddwbe) }, + { BPFBF_EBPFBE_INSN_XADDWBE, SEM_FN_NAME (bpfbf_ebpfbe,xaddwbe) }, + { BPFBF_EBPFBE_INSN_BRKPT, SEM_FN_NAME (bpfbf_ebpfbe,brkpt) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (bpfbf_ebpfbe,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + int mach_num = MACH_NUM (CPU_MACH (current_cpu)); + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { + const CGEN_INSN *insn = idesc_table[sf->index].idata; + int valid_p = (CGEN_INSN_VIRTUAL_P (insn) + || CGEN_INSN_MACH_HAS_P (insn, mach_num)); +#if FAST_P + if (valid_p) + idesc_table[sf->index].sem_fast = sf->fn; + else + idesc_table[sf->index].sem_fast = SEM_FN_NAME (bpfbf_ebpfbe,x_invalid); +#else + if (valid_p) + idesc_table[sf->index].sem_full = sf->fn; + else + idesc_table[sf->index].sem_full = SEM_FN_NAME (bpfbf_ebpfbe,x_invalid); +#endif + } +} + diff --git a/sim/bpf/sem-le.c b/sim/bpf/sem-le.c new file mode 100644 index 00000000000..8bb1debfb7f --- /dev/null +++ b/sim/bpf/sem-le.c @@ -0,0 +1,3207 @@ +/* Simulator instruction semantics for bpfbf. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright (C) 1996-2020 Free Software Foundation, Inc. + +This file is part of the GNU simulators. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#define WANT_CPU bpfbf +#define WANT_CPU_BPFBF + +#include "sim-main.h" +#include "cgen-mem.h" +#include "cgen-ops.h" + +#undef GET_ATTR +#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) + +/* This is used so that we can compile two copies of the semantic code, + one with full feature support and one without that runs fast(er). + FAST_P, when desired, is defined on the command line, -DFAST_P=1. */ +#if FAST_P +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn) +#undef CGEN_TRACE_RESULT +#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val) +#else +#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn) +#endif + +/* x-invalid: --invalid-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { + /* Update the recorded pc in the cpu state struct. + Only necessary for WITH_SCACHE case, but to avoid the + conditional compilation .... */ + SET_H_PC (pc); + /* Virtual insns have zero size. Overwrite vpc with address of next insn + using the default-insn-bitsize spec. When executing insns in parallel + we may want to queue the fault and continue execution. */ + vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); + } + + return vpc; +#undef FLD +} + +/* x-after: --after-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFLE + bpfbf_ebpfle_pbb_after (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-before: --before-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFLE + bpfbf_ebpfle_pbb_before (current_cpu, sem_arg); +#endif + } + + return vpc; +#undef FLD +} + +/* x-cti-chain: --cti-chain-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFLE +#ifdef DEFINE_SWITCH + vpc = bpfbf_ebpfle_pbb_cti_chain (current_cpu, sem_arg, + pbb_br_type, pbb_br_npc); + BREAK (sem); +#else + /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ + vpc = bpfbf_ebpfle_pbb_cti_chain (current_cpu, sem_arg, + CPU_PBB_BR_TYPE (current_cpu), + CPU_PBB_BR_NPC (current_cpu)); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-chain: --chain-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFLE + vpc = bpfbf_ebpfle_pbb_chain (current_cpu, sem_arg); +#ifdef DEFINE_SWITCH + BREAK (sem); +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* x-begin: --begin-- */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); + + { +#if WITH_SCACHE_PBB_BPFBF_EBPFLE +#if defined DEFINE_SWITCH || defined FAST_P + /* In the switch case FAST_P is a constant, allowing several optimizations + in any called inline functions. */ + vpc = bpfbf_ebpfle_pbb_begin (current_cpu, FAST_P); +#else +#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ + vpc = bpfbf_ebpfle_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); +#else + vpc = bpfbf_ebpfle_pbb_begin (current_cpu, 0); +#endif +#endif +#endif + } + + return vpc; +#undef FLD +} + +/* addile: add $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,addile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* addrle: add $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,addrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* add32ile: add32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,add32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ADDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* add32rle: add32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,add32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ADDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* subile: sub $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,subile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SUBDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* subrle: sub $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,subrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SUBDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* sub32ile: sub32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,sub32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SUBSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sub32rle: sub32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,sub32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SUBSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mulile: mul $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mulile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MULDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mulrle: mul $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mulrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MULDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mul32ile: mul32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mul32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MULSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mul32rle: mul32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mul32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MULSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* divile: div $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,divile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* divrle: div $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,divrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* div32ile: div32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,div32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* div32rle: div32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,div32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* orile: or $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,orile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ORDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* orrle: or $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,orrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ORDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* or32ile: or32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,or32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ORSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* or32rle: or32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,or32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ORSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* andile: and $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,andile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ANDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* andrle: and $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,andrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ANDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* and32ile: and32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,and32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ANDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* and32rle: and32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,and32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = ANDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lshile: lsh $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,lshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SLLDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lshrle: lsh $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,lshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SLLDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lsh32ile: lsh32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,lsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SLLSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* lsh32rle: lsh32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,lsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SLLSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* rshile: rsh $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,rshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRLDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* rshrle: rsh $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,rshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRLDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* rsh32ile: rsh32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,rsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRLSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* rsh32rle: rsh32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,rsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRLSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* modile: mod $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,modile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* modrle: mod $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,modrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mod32ile: mod32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mod32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mod32rle: mod32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mod32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xorile: xor $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xorile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = XORDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* xorrle: xor $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xorrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = XORDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* xor32ile: xor32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xor32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = XORSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* xor32rle: xor32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xor32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = XORSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* arshile: arsh $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,arshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRADI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* arshrle: arsh $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,arshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = SRADI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* arsh32ile: arsh32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,arsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRASI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* arsh32rle: arsh32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,arsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = SRASI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* negle: neg $dstle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,negle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = NEGDI (CPU (h_gpr[FLD (f_dstle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* neg32le: neg32 $dstle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,neg32le) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = NEGSI (CPU (h_gpr[FLD (f_dstle)])); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* movile: mov $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,movile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = FLD (f_imm32); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* movrle: mov $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,movrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = CPU (h_gpr[FLD (f_srcle)]); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* mov32ile: mov32 $dstle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mov32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = FLD (f_imm32); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* mov32rle: mov32 $dstle,$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,mov32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + USI opval = CPU (h_gpr[FLD (f_srcle)]); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* endlele: endle $dstle,$endsize */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,endlele) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = bpfbf_endle (current_cpu, CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* endbele: endbe $dstle,$endsize */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,endbele) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = bpfbf_endbe (current_cpu, CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32)); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* lddwle: lddw $dstle,$imm64 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,lddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_lddwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 16); + + { + DI opval = FLD (f_imm64); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsw: ldabsw $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsh: ldabsh $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldabsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsb: ldabsb $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldabsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldabsdw: ldabsdw $imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldabsdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldindwle: ldindw $srcle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldindwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldindhle: ldindh $srcle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldindhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldindble: ldindb $srcle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldindble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldinddwle: ldinddw $srcle,$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldinddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32)))); + CPU (h_gpr[((UINT) 0)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* ldxwle: ldxw $dstle,[$srcle+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldxwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxhle: ldxh $dstle,[$srcle+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldxhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = GETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxble: ldxb $dstle,[$srcle+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldxble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = GETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* ldxdwle: ldxdw $dstle,[$srcle+$offset16] */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ldxdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16))); + CPU (h_gpr[FLD (f_dstle)]) = opval; + CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* stxwle: stxw [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stxwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = CPU (h_gpr[FLD (f_srcle)]); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxhle: stxh [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stxhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = CPU (h_gpr[FLD (f_srcle)]); + SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxble: stxb [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stxble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = CPU (h_gpr[FLD (f_srcle)]); + SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stxdwle: stxdw [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stxdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = CPU (h_gpr[FLD (f_srcle)]); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* stble: stb [$dstle+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stble) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + QI opval = FLD (f_imm32); + SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* sthle: sth [$dstle+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,sthle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + HI opval = FLD (f_imm32); + SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stwle: stw [$dstle+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + SI opval = FLD (f_imm32); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } + + return vpc; +#undef FLD +} + +/* stdwle: stdw [$dstle+$offset16],$imm32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,stdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = FLD (f_imm32); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } + + return vpc; +#undef FLD +} + +/* jeqile: jeq $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jeqile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeqrle: jeq $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jeqrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeq32ile: jeq32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jeq32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jeq32rle: jeq32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jeq32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (EQSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgtile: jgt $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgtile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgtrle: jgt $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgtrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgt32ile: jgt32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgt32rle: jgt32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgeile: jge $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgeile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jgerle: jge $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jgerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jge32ile: jge32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jge32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jge32rle: jge32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jge32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jltile: jlt $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jltile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jltrle: jlt $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jltrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlt32ile: jlt32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jlt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlt32rle: jlt32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jlt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jleile: jle $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jleile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jlerle: jle $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jlerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jle32ile: jle32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jle32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jle32rle: jle32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jle32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsetile: jset $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsetile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsetrle: jset $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsetrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jset32ile: jset32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jset32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jset32rle: jset32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jset32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (ANDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jneile: jne $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jneile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jnerle: jne $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jnerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jne32ile: jne32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jne32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jne32rle: jne32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jne32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (NESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgtile: jsgt $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgtile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgtrle: jsgt $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgtrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgt32ile: jsgt32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgt32rle: jsgt32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GTSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgeile: jsge $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgeile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsgerle: jsge $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsgerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsge32ile: jsge32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsge32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsge32rle: jsge32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsge32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (GESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsltile: jslt $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsltile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsltrle: jslt $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsltrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslt32ile: jslt32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jslt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslt32rle: jslt32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jslt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LTSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsleile: jsle $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsleile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jslerle: jsle $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jslerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsle32ile: jsle32 $dstle,$imm32,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsle32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* jsle32rle: jsle32 $dstle,$srcle,$disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,jsle32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +if (LESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) { + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + written |= (1 << 4); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } +} + + abuf->written = written; + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* callle: call $disp32 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,callle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldindwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_call (current_cpu, FLD (f_imm32), FLD (f_srcle)); + + return vpc; +#undef FLD +} + +/* ja: ja $disp16 */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,ja) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_stble.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_BRANCH_INIT + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + + { + DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); + CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval); + } + + SEM_BRANCH_FINI (vpc); + return vpc; +#undef FLD +} + +/* exit: exit */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,exit) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_exit (current_cpu); + + return vpc; +#undef FLD +} + +/* xadddwle: xadddw [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xadddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +{ + DI tmp_tmp; + tmp_tmp = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16))); + { + DI opval = ADDDI (tmp_tmp, CPU (h_gpr[FLD (f_srcle)])); + SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval); + } +} + + return vpc; +#undef FLD +} + +/* xaddwle: xaddw [$dstle+$offset16],$srcle */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,xaddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_ldxwle.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +{ + SI tmp_tmp; + tmp_tmp = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16))); + { + SI opval = ADDSI (tmp_tmp, CPU (h_gpr[FLD (f_srcle)])); + SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval); + CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); + } +} + + return vpc; +#undef FLD +} + +/* brkpt: brkpt */ + +static SEM_PC +SEM_FN_NAME (bpfbf_ebpfle,brkpt) (SIM_CPU *current_cpu, SEM_ARG sem_arg) +{ +#define FLD(f) abuf->fields.sfmt_empty.f + ARGBUF *abuf = SEM_ARGBUF (sem_arg); + int UNUSED written = 0; + IADDR UNUSED pc = abuf->addr; + SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8); + +bpfbf_breakpoint (current_cpu); + + return vpc; +#undef FLD +} + +/* Table of all semantic fns. */ + +static const struct sem_fn_desc sem_fns[] = { + { BPFBF_EBPFLE_INSN_X_INVALID, SEM_FN_NAME (bpfbf_ebpfle,x_invalid) }, + { BPFBF_EBPFLE_INSN_X_AFTER, SEM_FN_NAME (bpfbf_ebpfle,x_after) }, + { BPFBF_EBPFLE_INSN_X_BEFORE, SEM_FN_NAME (bpfbf_ebpfle,x_before) }, + { BPFBF_EBPFLE_INSN_X_CTI_CHAIN, SEM_FN_NAME (bpfbf_ebpfle,x_cti_chain) }, + { BPFBF_EBPFLE_INSN_X_CHAIN, SEM_FN_NAME (bpfbf_ebpfle,x_chain) }, + { BPFBF_EBPFLE_INSN_X_BEGIN, SEM_FN_NAME (bpfbf_ebpfle,x_begin) }, + { BPFBF_EBPFLE_INSN_ADDILE, SEM_FN_NAME (bpfbf_ebpfle,addile) }, + { BPFBF_EBPFLE_INSN_ADDRLE, SEM_FN_NAME (bpfbf_ebpfle,addrle) }, + { BPFBF_EBPFLE_INSN_ADD32ILE, SEM_FN_NAME (bpfbf_ebpfle,add32ile) }, + { BPFBF_EBPFLE_INSN_ADD32RLE, SEM_FN_NAME (bpfbf_ebpfle,add32rle) }, + { BPFBF_EBPFLE_INSN_SUBILE, SEM_FN_NAME (bpfbf_ebpfle,subile) }, + { BPFBF_EBPFLE_INSN_SUBRLE, SEM_FN_NAME (bpfbf_ebpfle,subrle) }, + { BPFBF_EBPFLE_INSN_SUB32ILE, SEM_FN_NAME (bpfbf_ebpfle,sub32ile) }, + { BPFBF_EBPFLE_INSN_SUB32RLE, SEM_FN_NAME (bpfbf_ebpfle,sub32rle) }, + { BPFBF_EBPFLE_INSN_MULILE, SEM_FN_NAME (bpfbf_ebpfle,mulile) }, + { BPFBF_EBPFLE_INSN_MULRLE, SEM_FN_NAME (bpfbf_ebpfle,mulrle) }, + { BPFBF_EBPFLE_INSN_MUL32ILE, SEM_FN_NAME (bpfbf_ebpfle,mul32ile) }, + { BPFBF_EBPFLE_INSN_MUL32RLE, SEM_FN_NAME (bpfbf_ebpfle,mul32rle) }, + { BPFBF_EBPFLE_INSN_DIVILE, SEM_FN_NAME (bpfbf_ebpfle,divile) }, + { BPFBF_EBPFLE_INSN_DIVRLE, SEM_FN_NAME (bpfbf_ebpfle,divrle) }, + { BPFBF_EBPFLE_INSN_DIV32ILE, SEM_FN_NAME (bpfbf_ebpfle,div32ile) }, + { BPFBF_EBPFLE_INSN_DIV32RLE, SEM_FN_NAME (bpfbf_ebpfle,div32rle) }, + { BPFBF_EBPFLE_INSN_ORILE, SEM_FN_NAME (bpfbf_ebpfle,orile) }, + { BPFBF_EBPFLE_INSN_ORRLE, SEM_FN_NAME (bpfbf_ebpfle,orrle) }, + { BPFBF_EBPFLE_INSN_OR32ILE, SEM_FN_NAME (bpfbf_ebpfle,or32ile) }, + { BPFBF_EBPFLE_INSN_OR32RLE, SEM_FN_NAME (bpfbf_ebpfle,or32rle) }, + { BPFBF_EBPFLE_INSN_ANDILE, SEM_FN_NAME (bpfbf_ebpfle,andile) }, + { BPFBF_EBPFLE_INSN_ANDRLE, SEM_FN_NAME (bpfbf_ebpfle,andrle) }, + { BPFBF_EBPFLE_INSN_AND32ILE, SEM_FN_NAME (bpfbf_ebpfle,and32ile) }, + { BPFBF_EBPFLE_INSN_AND32RLE, SEM_FN_NAME (bpfbf_ebpfle,and32rle) }, + { BPFBF_EBPFLE_INSN_LSHILE, SEM_FN_NAME (bpfbf_ebpfle,lshile) }, + { BPFBF_EBPFLE_INSN_LSHRLE, SEM_FN_NAME (bpfbf_ebpfle,lshrle) }, + { BPFBF_EBPFLE_INSN_LSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,lsh32ile) }, + { BPFBF_EBPFLE_INSN_LSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,lsh32rle) }, + { BPFBF_EBPFLE_INSN_RSHILE, SEM_FN_NAME (bpfbf_ebpfle,rshile) }, + { BPFBF_EBPFLE_INSN_RSHRLE, SEM_FN_NAME (bpfbf_ebpfle,rshrle) }, + { BPFBF_EBPFLE_INSN_RSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,rsh32ile) }, + { BPFBF_EBPFLE_INSN_RSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,rsh32rle) }, + { BPFBF_EBPFLE_INSN_MODILE, SEM_FN_NAME (bpfbf_ebpfle,modile) }, + { BPFBF_EBPFLE_INSN_MODRLE, SEM_FN_NAME (bpfbf_ebpfle,modrle) }, + { BPFBF_EBPFLE_INSN_MOD32ILE, SEM_FN_NAME (bpfbf_ebpfle,mod32ile) }, + { BPFBF_EBPFLE_INSN_MOD32RLE, SEM_FN_NAME (bpfbf_ebpfle,mod32rle) }, + { BPFBF_EBPFLE_INSN_XORILE, SEM_FN_NAME (bpfbf_ebpfle,xorile) }, + { BPFBF_EBPFLE_INSN_XORRLE, SEM_FN_NAME (bpfbf_ebpfle,xorrle) }, + { BPFBF_EBPFLE_INSN_XOR32ILE, SEM_FN_NAME (bpfbf_ebpfle,xor32ile) }, + { BPFBF_EBPFLE_INSN_XOR32RLE, SEM_FN_NAME (bpfbf_ebpfle,xor32rle) }, + { BPFBF_EBPFLE_INSN_ARSHILE, SEM_FN_NAME (bpfbf_ebpfle,arshile) }, + { BPFBF_EBPFLE_INSN_ARSHRLE, SEM_FN_NAME (bpfbf_ebpfle,arshrle) }, + { BPFBF_EBPFLE_INSN_ARSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,arsh32ile) }, + { BPFBF_EBPFLE_INSN_ARSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,arsh32rle) }, + { BPFBF_EBPFLE_INSN_NEGLE, SEM_FN_NAME (bpfbf_ebpfle,negle) }, + { BPFBF_EBPFLE_INSN_NEG32LE, SEM_FN_NAME (bpfbf_ebpfle,neg32le) }, + { BPFBF_EBPFLE_INSN_MOVILE, SEM_FN_NAME (bpfbf_ebpfle,movile) }, + { BPFBF_EBPFLE_INSN_MOVRLE, SEM_FN_NAME (bpfbf_ebpfle,movrle) }, + { BPFBF_EBPFLE_INSN_MOV32ILE, SEM_FN_NAME (bpfbf_ebpfle,mov32ile) }, + { BPFBF_EBPFLE_INSN_MOV32RLE, SEM_FN_NAME (bpfbf_ebpfle,mov32rle) }, + { BPFBF_EBPFLE_INSN_ENDLELE, SEM_FN_NAME (bpfbf_ebpfle,endlele) }, + { BPFBF_EBPFLE_INSN_ENDBELE, SEM_FN_NAME (bpfbf_ebpfle,endbele) }, + { BPFBF_EBPFLE_INSN_LDDWLE, SEM_FN_NAME (bpfbf_ebpfle,lddwle) }, + { BPFBF_EBPFLE_INSN_LDABSW, SEM_FN_NAME (bpfbf_ebpfle,ldabsw) }, + { BPFBF_EBPFLE_INSN_LDABSH, SEM_FN_NAME (bpfbf_ebpfle,ldabsh) }, + { BPFBF_EBPFLE_INSN_LDABSB, SEM_FN_NAME (bpfbf_ebpfle,ldabsb) }, + { BPFBF_EBPFLE_INSN_LDABSDW, SEM_FN_NAME (bpfbf_ebpfle,ldabsdw) }, + { BPFBF_EBPFLE_INSN_LDINDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldindwle) }, + { BPFBF_EBPFLE_INSN_LDINDHLE, SEM_FN_NAME (bpfbf_ebpfle,ldindhle) }, + { BPFBF_EBPFLE_INSN_LDINDBLE, SEM_FN_NAME (bpfbf_ebpfle,ldindble) }, + { BPFBF_EBPFLE_INSN_LDINDDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldinddwle) }, + { BPFBF_EBPFLE_INSN_LDXWLE, SEM_FN_NAME (bpfbf_ebpfle,ldxwle) }, + { BPFBF_EBPFLE_INSN_LDXHLE, SEM_FN_NAME (bpfbf_ebpfle,ldxhle) }, + { BPFBF_EBPFLE_INSN_LDXBLE, SEM_FN_NAME (bpfbf_ebpfle,ldxble) }, + { BPFBF_EBPFLE_INSN_LDXDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldxdwle) }, + { BPFBF_EBPFLE_INSN_STXWLE, SEM_FN_NAME (bpfbf_ebpfle,stxwle) }, + { BPFBF_EBPFLE_INSN_STXHLE, SEM_FN_NAME (bpfbf_ebpfle,stxhle) }, + { BPFBF_EBPFLE_INSN_STXBLE, SEM_FN_NAME (bpfbf_ebpfle,stxble) }, + { BPFBF_EBPFLE_INSN_STXDWLE, SEM_FN_NAME (bpfbf_ebpfle,stxdwle) }, + { BPFBF_EBPFLE_INSN_STBLE, SEM_FN_NAME (bpfbf_ebpfle,stble) }, + { BPFBF_EBPFLE_INSN_STHLE, SEM_FN_NAME (bpfbf_ebpfle,sthle) }, + { BPFBF_EBPFLE_INSN_STWLE, SEM_FN_NAME (bpfbf_ebpfle,stwle) }, + { BPFBF_EBPFLE_INSN_STDWLE, SEM_FN_NAME (bpfbf_ebpfle,stdwle) }, + { BPFBF_EBPFLE_INSN_JEQILE, SEM_FN_NAME (bpfbf_ebpfle,jeqile) }, + { BPFBF_EBPFLE_INSN_JEQRLE, SEM_FN_NAME (bpfbf_ebpfle,jeqrle) }, + { BPFBF_EBPFLE_INSN_JEQ32ILE, SEM_FN_NAME (bpfbf_ebpfle,jeq32ile) }, + { BPFBF_EBPFLE_INSN_JEQ32RLE, SEM_FN_NAME (bpfbf_ebpfle,jeq32rle) }, + { BPFBF_EBPFLE_INSN_JGTILE, SEM_FN_NAME (bpfbf_ebpfle,jgtile) }, + { BPFBF_EBPFLE_INSN_JGTRLE, SEM_FN_NAME (bpfbf_ebpfle,jgtrle) }, + { BPFBF_EBPFLE_INSN_JGT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jgt32ile) }, + { BPFBF_EBPFLE_INSN_JGT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jgt32rle) }, + { BPFBF_EBPFLE_INSN_JGEILE, SEM_FN_NAME (bpfbf_ebpfle,jgeile) }, + { BPFBF_EBPFLE_INSN_JGERLE, SEM_FN_NAME (bpfbf_ebpfle,jgerle) }, + { BPFBF_EBPFLE_INSN_JGE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jge32ile) }, + { BPFBF_EBPFLE_INSN_JGE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jge32rle) }, + { BPFBF_EBPFLE_INSN_JLTILE, SEM_FN_NAME (bpfbf_ebpfle,jltile) }, + { BPFBF_EBPFLE_INSN_JLTRLE, SEM_FN_NAME (bpfbf_ebpfle,jltrle) }, + { BPFBF_EBPFLE_INSN_JLT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jlt32ile) }, + { BPFBF_EBPFLE_INSN_JLT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jlt32rle) }, + { BPFBF_EBPFLE_INSN_JLEILE, SEM_FN_NAME (bpfbf_ebpfle,jleile) }, + { BPFBF_EBPFLE_INSN_JLERLE, SEM_FN_NAME (bpfbf_ebpfle,jlerle) }, + { BPFBF_EBPFLE_INSN_JLE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jle32ile) }, + { BPFBF_EBPFLE_INSN_JLE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jle32rle) }, + { BPFBF_EBPFLE_INSN_JSETILE, SEM_FN_NAME (bpfbf_ebpfle,jsetile) }, + { BPFBF_EBPFLE_INSN_JSETRLE, SEM_FN_NAME (bpfbf_ebpfle,jsetrle) }, + { BPFBF_EBPFLE_INSN_JSET32ILE, SEM_FN_NAME (bpfbf_ebpfle,jset32ile) }, + { BPFBF_EBPFLE_INSN_JSET32RLE, SEM_FN_NAME (bpfbf_ebpfle,jset32rle) }, + { BPFBF_EBPFLE_INSN_JNEILE, SEM_FN_NAME (bpfbf_ebpfle,jneile) }, + { BPFBF_EBPFLE_INSN_JNERLE, SEM_FN_NAME (bpfbf_ebpfle,jnerle) }, + { BPFBF_EBPFLE_INSN_JNE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jne32ile) }, + { BPFBF_EBPFLE_INSN_JNE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jne32rle) }, + { BPFBF_EBPFLE_INSN_JSGTILE, SEM_FN_NAME (bpfbf_ebpfle,jsgtile) }, + { BPFBF_EBPFLE_INSN_JSGTRLE, SEM_FN_NAME (bpfbf_ebpfle,jsgtrle) }, + { BPFBF_EBPFLE_INSN_JSGT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsgt32ile) }, + { BPFBF_EBPFLE_INSN_JSGT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsgt32rle) }, + { BPFBF_EBPFLE_INSN_JSGEILE, SEM_FN_NAME (bpfbf_ebpfle,jsgeile) }, + { BPFBF_EBPFLE_INSN_JSGERLE, SEM_FN_NAME (bpfbf_ebpfle,jsgerle) }, + { BPFBF_EBPFLE_INSN_JSGE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsge32ile) }, + { BPFBF_EBPFLE_INSN_JSGE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsge32rle) }, + { BPFBF_EBPFLE_INSN_JSLTILE, SEM_FN_NAME (bpfbf_ebpfle,jsltile) }, + { BPFBF_EBPFLE_INSN_JSLTRLE, SEM_FN_NAME (bpfbf_ebpfle,jsltrle) }, + { BPFBF_EBPFLE_INSN_JSLT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jslt32ile) }, + { BPFBF_EBPFLE_INSN_JSLT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jslt32rle) }, + { BPFBF_EBPFLE_INSN_JSLEILE, SEM_FN_NAME (bpfbf_ebpfle,jsleile) }, + { BPFBF_EBPFLE_INSN_JSLERLE, SEM_FN_NAME (bpfbf_ebpfle,jslerle) }, + { BPFBF_EBPFLE_INSN_JSLE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsle32ile) }, + { BPFBF_EBPFLE_INSN_JSLE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsle32rle) }, + { BPFBF_EBPFLE_INSN_CALLLE, SEM_FN_NAME (bpfbf_ebpfle,callle) }, + { BPFBF_EBPFLE_INSN_JA, SEM_FN_NAME (bpfbf_ebpfle,ja) }, + { BPFBF_EBPFLE_INSN_EXIT, SEM_FN_NAME (bpfbf_ebpfle,exit) }, + { BPFBF_EBPFLE_INSN_XADDDWLE, SEM_FN_NAME (bpfbf_ebpfle,xadddwle) }, + { BPFBF_EBPFLE_INSN_XADDWLE, SEM_FN_NAME (bpfbf_ebpfle,xaddwle) }, + { BPFBF_EBPFLE_INSN_BRKPT, SEM_FN_NAME (bpfbf_ebpfle,brkpt) }, + { 0, 0 } +}; + +/* Add the semantic fns to IDESC_TABLE. */ + +void +SEM_FN_NAME (bpfbf_ebpfle,init_idesc_table) (SIM_CPU *current_cpu) +{ + IDESC *idesc_table = CPU_IDESC (current_cpu); + const struct sem_fn_desc *sf; + int mach_num = MACH_NUM (CPU_MACH (current_cpu)); + + for (sf = &sem_fns[0]; sf->fn != 0; ++sf) + { + const CGEN_INSN *insn = idesc_table[sf->index].idata; + int valid_p = (CGEN_INSN_VIRTUAL_P (insn) + || CGEN_INSN_MACH_HAS_P (insn, mach_num)); +#if FAST_P + if (valid_p) + idesc_table[sf->index].sem_fast = sf->fn; + else + idesc_table[sf->index].sem_fast = SEM_FN_NAME (bpfbf_ebpfle,x_invalid); +#else + if (valid_p) + idesc_table[sf->index].sem_full = sf->fn; + else + idesc_table[sf->index].sem_full = SEM_FN_NAME (bpfbf_ebpfle,x_invalid); +#endif + } +} +