From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Apr 2019 16:04:51 +0000 (+0100)
Subject: try bi-directional flatten
X-Git-Tag: ls180-24jan2020~1257
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c4dbc97ff085c16dec9ab1b42bac6f7f0977f3b;p=ieee754fpu.git

try bi-directional flatten
---

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index b3194962..4dbe817a 100644
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -10,19 +10,19 @@ class RecordTest:
 
     def __init__(self):
         self.r1 = RecordObject()
-        self.r1.sig1 = Signal(32)
+        self.r1.sig1 = Signal(16)
         self.r1.r2 = RecordObject()
-        self.r1.r2.sig2 = Signal(32)
+        self.r1.r2.sig2 = Signal(16)
         self.r1.r3 = RecordObject()
-        self.r1.r3.sig3 = Signal(32)
-        self.sig123 = Signal(96)
+        self.r1.r3.sig3 = Signal(16)
+        self.sig123 = Signal(48)
 
     def elaborate(self, platform):
         m = Module()
 
-        sig1 = Signal(32)
+        sig1 = Signal(16)
         m.d.comb += sig1.eq(self.r1.sig1)
-        sig2 = Signal(32)
+        sig2 = Signal(16)
         m.d.comb += sig2.eq(self.r1.r2.sig2)
 
         print (self.r1.fields)
@@ -36,12 +36,53 @@ class RecordTest:
 def testbench(dut):
     yield dut.r1.sig1.eq(5)
     yield dut.r1.r2.sig2.eq(10)
+    yield dut.r1.r3.sig3.eq(1)
     
     sig1 = yield dut.r1.sig1
     assert sig1 == 5
     sig2 = yield dut.r1.r2.sig2
     assert sig2 == 10
 
+    yield
+
+    sig123 = yield dut.sig123
+    print ("sig123", hex(sig123))
+    assert sig123 == 0x1000a0005
+
+
+
+class RecordTest2:
+
+    def __init__(self):
+        self.r1 = RecordObject()
+        self.r1.sig1 = Signal(16)
+        self.r1.r2 = RecordObject()
+        self.r1.r2.sig2 = Signal(16)
+        self.r1.r3 = RecordObject()
+        self.r1.r3.sig3 = Signal(16)
+        self.sig123 = Signal(48)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.d.comb += flatten(self.r1).eq(self.sig123)
+
+        return m
+
+
+def testbench2(dut):
+    
+    sig123 = yield dut.sig123.eq(0x1000a0005)
+
+    yield
+
+    sig1 = yield dut.r1.sig1
+    assert sig1 == 5
+    sig2 = yield dut.r1.r2.sig2
+    assert sig2 == 10
+    sig3 = yield dut.r1.r3.sig3
+    assert sig3 == 1
+
 
 
 ######################################################################
@@ -56,3 +97,10 @@ if __name__ == '__main__':
     with open("test_record1.il", "w") as f:
         f.write(vl)
 
+    print ("test 2")
+    dut = RecordTest2()
+    run_simulation(dut, testbench2(dut), vcd_name="test_record2.vcd")
+    vl = rtlil.convert(dut, ports=[dut.sig123, dut.r1.sig1, dut.r1.r2.sig2])
+    with open("test_record2.il", "w") as f:
+        f.write(vl)
+