From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Oct 2014 19:53:26 +0000 (+0100)
Subject: add input pipe stage option
X-Git-Tag: 24jan2021_ls180~2575^2~51
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c5c32751ebf52cb79016df7e8df5ecab2f9091f;p=litex.git

add input pipe stage option
---

diff --git a/miscope/mila.py b/miscope/mila.py
index 765ac840..abf8e79c 100644
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -18,10 +18,11 @@ def _getattr_all(l, attr):
 	return r
 
 class MiLa(Module, AutoCSR):
-	def __init__(self, depth, dat, with_rle=False, clk_domain="sys"):
+	def __init__(self, depth, dat, with_rle=False, clk_domain="sys", pipe=False):
 		self.depth = depth
 		self.with_rle = with_rle
 		self.clk_domain = clk_domain
+		self.pipe = pipe
 		self.ports = []
 		self.width = flen(dat)
 
@@ -33,12 +34,25 @@ class MiLa(Module, AutoCSR):
 		self.ports.append(port)
 
 	def do_finalize(self):
+		stb = self.stb
+		dat = self.dat
+		if self.pipe:
+			sync = getattr(self.sync, self.clk_domain)
+			stb_new = Signal()
+			dat_new = Signal(flen(dat))
+			sync += [
+				stb_new.eq(stb),
+				dat_new.eq(dat)
+			]
+			stb = stb_new
+			dat = dat_new
+
 		if self.clk_domain is not "sys":
 			fifo = AsyncFIFO([("dat", self.width)], 32)
 			self.submodules += RenameClockDomains(fifo, {"write": self.clk_domain, "read": "sys"})
 			self.comb += [
-				fifo.sink.stb.eq(self.stb),
-				fifo.sink.dat.eq(self.dat)
+				fifo.sink.stb.eq(stb),
+				fifo.sink.dat.eq(dat)
 			]
 			sink = Record(dat_layout(self.width))
 			self.comb += [
@@ -49,8 +63,8 @@ class MiLa(Module, AutoCSR):
 		else:
 			sink = Record(dat_layout(self.width))
 			self.comb += [
-				sink.stb.eq(self.stb),
-				sink.dat.eq(self.dat)
+				sink.stb.eq(stb),
+				sink.dat.eq(dat)
 			]
 
 		self.submodules.trigger = trigger = Trigger(self.width, self.ports)