From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 18:14:59 +0000 (-0700)
Subject: Revert "Add abc_box_id attribute to MUXF7/F8 cells"
X-Git-Tag: working-ls180~1208^2~345
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c6cf07acff290ab2132c1a7d262bf195fa85b8b;p=yosys.git

Revert "Add abc_box_id attribute to MUXF7/F8 cells"

This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 05dd9229f..0c8f282a4 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -159,12 +159,10 @@ module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
 
-(* abc_box_id = 1 *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc_box_id = 2 *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule