From: bugzilla-daemon Date: Mon, 8 Jun 2020 18:52:51 +0000 (+0000) Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt,... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c88f40e04460553e2bab49d65a5cc1ea291f39a;p=libre-riscv-dev.git [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side --- diff --git a/c4/5e21b6164fc485fd81e0772e0d6984d0c2f3c5 b/c4/5e21b6164fc485fd81e0772e0d6984d0c2f3c5 new file mode 100644 index 0000000..3913fa7 --- /dev/null +++ b/c4/5e21b6164fc485fd81e0772e0d6984d0c2f3c5 @@ -0,0 +1,70 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Mon, 08 Jun 2020 19:52:54 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jiMtA-0006bg-Vk; Mon, 08 Jun 2020 19:52:52 +0100 +Received: from localhost ([127.0.0.1] helo=bugs.libre-soc.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jiMt9-0006bY-AF + for libre-riscv-dev@lists.libre-riscv.org; Mon, 08 Jun 2020 19:52:51 +0100 +From: bugzilla-daemon@libre-soc.org +To: libre-riscv-dev@lists.libre-riscv.org +Date: Mon, 08 Jun 2020 18:52:51 +0000 +X-Bugzilla-Reason: CC +X-Bugzilla-Type: changed +X-Bugzilla-Watch-Reason: None +X-Bugzilla-Product: Libre-SOC's first SoC +X-Bugzilla-Component: Source Code +X-Bugzilla-Version: unspecified +X-Bugzilla-Keywords: +X-Bugzilla-Severity: enhancement +X-Bugzilla-Who: mtnolan2640@gmail.com +X-Bugzilla-Status: CONFIRMED +X-Bugzilla-Resolution: +X-Bugzilla-Priority: --- +X-Bugzilla-Assigned-To: lkcl@lkcl.net +X-Bugzilla-Flags: +X-Bugzilla-Changed-Fields: cc +Message-ID: +In-Reply-To: +References: +X-Bugzilla-URL: https://bugs.libre-soc.org/ +Auto-Submitted: auto-generated +MIME-Version: 1.0 +Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, + microwatt, simulator, side-by-side +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +aHR0cHM6Ly9idWdzLmxpYnJlLXNvYy5vcmcvc2hvd19idWcuY2dpP2lkPTM3MAoKTWljaGFlbCBO +b2xhbiA8bXRub2xhbjI2NDBAZ21haWwuY29tPiBjaGFuZ2VkOgoKICAgICAgICAgICBXaGF0ICAg +IHxSZW1vdmVkICAgICAgICAgICAgICAgICAgICAgfEFkZGVkCi0tLS0tLS0tLS0tLS0tLS0tLS0t +LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0K +ICAgICAgICAgICAgICAgICBDQ3wgICAgICAgICAgICAgICAgICAgICAgICAgICAgfG10bm9sYW4y +NjQwQGdtYWlsLmNvbQoKLS0tIENvbW1lbnQgIzEgZnJvbSBNaWNoYWVsIE5vbGFuIDxtdG5vbGFu +MjY0MEBnbWFpbC5jb20+IC0tLQpDeWNsZSBhY2N1cmF0ZSAtIGFzIGluIGNoZWNraW5nIHRoYXQg +dGhlIHJlc3VsdHMgYXJlIHRoZSBzYW1lIGFmdGVyIGV2ZXJ5IHN0ZXA/CgotLSAKWW91IGFyZSBy +ZWNlaXZpbmcgdGhpcyBtYWlsIGJlY2F1c2U6CllvdSBhcmUgb24gdGhlIENDIGxpc3QgZm9yIHRo +ZSBidWcuCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxp +YnJlLXJpc2N2LWRldiBtYWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxpc3RzLmxpYnJlLXJp +c2N2Lm9yZwpodHRwOi8vbGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4vbGlzdGluZm8vbGli +cmUtcmlzY3YtZGV2Cg== +