From: Florent Kermarrec Date: Mon, 23 Sep 2019 08:15:27 +0000 (+0200) Subject: soc_sdram: change l2_size checks order X-Git-Tag: 24jan2021_ls180~997 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8c979565a8b26f7ce6a491be641e11d9ba1ca2ed;p=litex.git soc_sdram: change l2_size checks order --- diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index a28b9bc3..ae4455af 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -82,8 +82,8 @@ class SoCSDRAM(SoCCore): geom_settings.colbits)*phy.settings.databits//8 main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now - l2_size = 2**int(log2(self.l2_size)) # Round to nearest power of 2 - l2_size = max(l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower + l2_size = max(self.l2_size, int(2*port.data_width/8)) # L2 has a minimal size, use it if lower + l2_size = 2**int(log2(l2_size)) # Round to nearest power of 2 # SoC <--> L2 Cache Wishbone interface ----------------------------------------------------- wb_sdram = wishbone.Interface()