From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Jun 2020 14:50:35 +0000 (+0100)
Subject: error in address width (truncated) in setting up L0CacheBuffer
X-Git-Tag: div_pipeline~382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ca22a5a5be4e62f20c21b2eb2731aef9e6e10c2;p=soc.git

error in address width (truncated) in setting up L0CacheBuffer
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index aadd4f48..ae5aea75 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -498,7 +498,7 @@ class L0CacheBuffer(Elaboratable):
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, n_units=3, regwid=16, addrwid=4):
         self.mem = TestMemory(regwid, addrwid, granularity=regwid//8)
-        self.l0 = L0CacheBuffer(n_units, self.mem, regwid, addrwid)
+        self.l0 = L0CacheBuffer(n_units, self.mem, regwid, addrwid<<1)
 
     def elaborate(self, platform):
         m = Module()