From: Mateusz Holenko <mholenko@antmicro.com>
Date: Mon, 6 May 2019 14:49:21 +0000 (+0200)
Subject: cpu: add `reserved_interrupts` property
X-Git-Tag: 24jan2021_ls180~1233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8caa38bc256da5098f969449b44662d63e3672fb;p=litex.git

cpu: add `reserved_interrupts` property
---

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 70d202ab..7b5d9272 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -33,6 +33,10 @@ class LM32(Module):
     def linker_output_format(self):
         return "elf32-lm32"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, eba_reset, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 3c3c41d6..73279aba 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -31,6 +31,10 @@ class Minerva(Module):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, cpu_reset_address, variant="standard"):
         assert variant is "standard", "Unsupported variant %s" % variant
         self.platform = platform
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index bb46a6a6..82926e06 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -47,6 +47,10 @@ class MOR1KX(Module):
     def linker_output_format(self):
         return "elf32-or1k"
 
+    @property
+    def reserved_interrupts(self):
+        return { "nmi": 0 }
+
     def __init__(self, platform, reset_pc, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 846ab07d..332b768e 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -45,6 +45,10 @@ class PicoRV32(Module):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return { "picorv32_timer": 0, "picorv32_ebreak_ecall_illegal": 1, "picorv32_bus_error": 2 }
+
     def __init__(self, platform, progaddr_reset, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index de30de8d..3d904f86 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -81,6 +81,10 @@ class VexRiscv(Module, AutoCSR):
     def linker_output_format(self):
         return "elf32-littleriscv"
 
+    @property
+    def reserved_interrupts(self):
+        return {}
+
     def __init__(self, platform, cpu_reset_address, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform = platform