From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Feb 2020 17:57:59 +0000 (+0000)
Subject: add clk and ck so that ck is recognised for routing
X-Git-Tag: partial-core-ls180-gdsii~203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8cb69e6178ed0a4c3b43803095dfd1531c998cc7;p=soclayout.git

add clk and ck so that ck is recognised for routing
---

diff --git a/experiments4/coriolis2/settings.py b/experiments4/coriolis2/settings.py
index f93e33d..85b6b47 100644
--- a/experiments4/coriolis2/settings.py
+++ b/experiments4/coriolis2/settings.py
@@ -48,7 +48,7 @@ env = af.getEnvironment()
 env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
 #env.setCLOCK( '^clk$|m_clock' )
-env.setCLOCK( 'clk' )
+env.setCLOCK( 'clk|ck|cki' )
 env.setPOWER( 'vdd' )
 env.setGROUND( 'vss' )