From: lkcl <lkcl@web>
Date: Thu, 7 Jul 2022 08:07:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1308
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8cc0862cdc33b22558a917e466d87e185ebb9cc8;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 8ad8f23a4..3d8d4bc30 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -234,7 +234,7 @@ differences.  Form is `RM-1P-3S1D` where RS-as-source has a separate
 SVP64 designation from RS-as-dest. This gives a limited range of
 non-overwrite capability.
 
-# shift-and-add
+# shift-and-add <a name="shift-add"> </a>
 
 Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
 Too complex to add more LD/ST, a compromise is to add shift-and-add.