From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 17 Jul 2020 16:22:56 +0000 (+0200)
Subject: Use nMigen's XDR for DDR clk
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8cc2b544992419ecf810b8db88c2df87eb6a6430;p=gram.git

Use nMigen's XDR for DDR clk
---

diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py
index 38ceb1a..0f8cd41 100644
--- a/examples/headless-ecpix5.py
+++ b/examples/headless-ecpix5.py
@@ -32,7 +32,9 @@ class DDR3SoC(SoC, Elaboratable):
 
         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
 
-        self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))
+        ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
+            xdr={"clk":4})
+        self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
         ddrmodule = MT41K256M16(platform.default_clk_frequency, "1:2")
diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index ea18293..33fd2bd 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -169,17 +169,15 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
         rddata_en = Signal(self.settings.read_latency)
 
         # Clock --------------------------------------------------------------------------------
-        for i in range(len(self.pads.clk.o)):
-            m.submodules += Instance("ODDRX2F",
-                                     i_RST=ResetSignal("dramsync"),
-                                     i_ECLK=ClockSignal("sync2x"),
-                                     i_SCLK=ClockSignal(),
-                                     i_D0=0,
-                                     i_D1=1,
-                                     i_D2=0,
-                                     i_D3=1,
-                                     o_Q=self.pads.clk.o[i]
-                                     )
+        for i in range(len(self.pads.clk.o0)):
+            m.d.comb += [
+                self.pads.clk.o_clk[i].eq(ClockSignal("dramsync")),
+                self.pads.clk.o_fclk[i].eq(ClockSignal("sync2x")),
+                self.pads.clk.o0[i].eq(0),
+                self.pads.clk.o1[i].eq(1),
+                self.pads.clk.o2[i].eq(0),
+                self.pads.clk.o3[i].eq(1)
+            ]
 
         # Addresses and Commands ---------------------------------------------------------------
         for i in range(addressbits):
diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 486b831..d932d8b 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -29,7 +29,9 @@ class DDR3SoC(SoC, Elaboratable):
         self.ub = UARTBridge(divisor=5, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
-        self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"})))
+        ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
+            xdr={"clk":4})
+        self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
         ddrmodule = MT41K256M16(clk_freq, "1:2")