From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 16 Jan 2015 16:51:17 +0000 (+0100)
Subject: Bugfix in dff2dffe
X-Git-Tag: yosys-0.5~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8ce8a230f458d09f1847ba87a3073cf4c07579d3;p=yosys.git

Bugfix in dff2dffe
---

diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 339007156..17549bd06 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -173,7 +173,7 @@ struct Dff2dffeWorker
 			return or_input;
 
 		RTLIL::SigSpec y = module->addWire(NEW_ID);
-		RTLIL::Cell *c = module->addReduceOr(NEW_ID, or_input, y);
+		RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
 
 		if (make_gates) {
 			simplemap(module, c);