From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 15 Jul 2010 09:11:56 +0000 (-0700)
Subject: ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.
X-Git-Tag: stable_2012_02_02~994
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8cec87056824782e061eac152b83432899d9b6d9;p=gem5.git

ARM: Make an SRS instruction with a bad mode cause an undefined instruction fault.
---

diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 59a6f126a..f7830eff3 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -282,6 +282,8 @@ def format Thumb32SrsRfe() {{
             }
         } else {
             const uint32_t mode = bits(machInst, 4, 0);
+            if (badMode((OperatingMode)mode))
+                return new Unknown(machInst);
             if (!add && !wb) {
                 return new %(srs)s(machInst, mode,
                         SrsOp::DecrementBefore, wb);
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index f4cc16262..4fa707b2b 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -166,6 +166,8 @@ def format ArmUnconditional() {{
                     const uint32_t val = ((machInst >> 20) & 0x5);
                     if (val == 0x4) {
                         const uint32_t mode = bits(machInst, 4, 0);
+                        if (badMode((OperatingMode)mode))
+                            return new Unknown(machInst);
                         switch (bits(machInst, 24, 21)) {
                           case 0x2:
                             return new %(srs)s(machInst, mode,