From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 11 Oct 2022 09:48:29 +0000 (+0100)
Subject: add experimental post-increment fixedload pseudocode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8cfe36d0033ada8823c85e295add13ff5912cbe8;p=openpower-isa.git

add experimental post-increment fixedload pseudocode
---

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
new file mode 100644
index 00000000..3f74981d
--- /dev/null
+++ b/openpower/isa/pifixedload.mdwn
@@ -0,0 +1,186 @@
+<!-- This defines DRAFT instructions that are to be proposed for SV -->
+
+<!-- This defines instructions that load from RAM to a register -->
+<!-- Effective Address is always RA, and the usual EA is stored late in RA -->
+
+<!-- Note that these pages also define equivalent store instructions, -->
+<!-- these are described in fixedstore.mdwn -->
+
+
+
+# Load Byte and Zero with Post-Update
+
+D-Form
+
+* lbzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+# Load Byte and Zero with Post-Update Indexed
+
+X-Form
+
+* lbzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword and Zero with Post-Update
+
+D-Form
+
+* lhzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword and Zero with Post-Update Indexed
+
+X-Form
+
+* lhzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword Algebraic with Post-Update
+
+D-Form
+
+* lhaup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+# Load Halfword Algebraic with Post-Update Indexed
+
+X-Form
+
+* lhaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 2))
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+# Load Word and Zero with Post-Update
+
+D-Form
+
+* lwzup RT,D(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0]*32 || MEM(EA, 4)
+    RA <- (RA) + EXTS(D)
+
+Special Registers Altered:
+
+    None
+
+# Load Word and Zero with Post-Update Indexed
+
+X-Form
+
+* lwzupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- [0] * 32 || MEM(EA, 4)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+# Load Word Algebraic with Post-Update Indexed
+
+X-Form
+
+* lwaupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- EXTS(MEM(EA, 4))
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+
+# Load Doubleword with Post-Update Indexed
+
+DS-Form
+
+* ldup RT,DS(RA)
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + EXTS(DS || 0b00)
+
+Special Registers Altered:
+
+    None
+
+# Load Doubleword with Post-Update Indexed
+
+X-Form
+
+* ldupx RT,RA,RB
+
+Pseudo-code:
+
+    EA <- (RA)
+    RT <- MEM(EA, 8)
+    RA <- (RA) + (RB)
+
+Special Registers Altered:
+
+    None
+