From: Luke Kenneth Casson Leighton Date: Thu, 8 Sep 2022 23:01:39 +0000 (+0100) Subject: add binary interoperability section to rfc ls001 X-Git-Tag: opf_rfc_ls005_v1~583 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d09467a4481bc526c05588acbe47eee2add47a9;p=libreriscv.git add binary interoperability section to rfc ls001 --- diff --git a/openpower/sv/rfc/Makefile b/openpower/sv/rfc/Makefile index 0f091e013..24b4e0960 100644 --- a/openpower/sv/rfc/Makefile +++ b/openpower/sv/rfc/Makefile @@ -3,4 +3,5 @@ all: ls001.pdf ls001.pdf: ls001.mdwn pandoc -V geometry:margin=0.25in \ -V fontsize=9pt \ + -V papersize=a4 \ -f markdown ls001.mdwn -s -o ls001.pdf diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 60e27cd99..101ce3467 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -61,6 +61,20 @@ the two types of Compliancy Levels*. The resources below therefore are not all required for all SV Compliancy Levels but they are all required to be reserved. +# Binary Interoperability + +Power ISA is long-term stable. A catastrophic mistake has been made in +ARM SVE/2 and RISC-V RVV: "Silicon-Partner" Scalability, marketed as +a feature, allows the same instructions to mean different things on +different implementations (a different Vector bitwidth). This means +that binary interoperability is not only impossible to achieve but +Illegal Instruction trap-and-emulate is also out of the question. + +**Simple-V guarantees binary interoperability** by defining fixed +register file bitwidths and size for all instructions. This does +mean that **reserved** space is important to have in SVP64, in order +to provide future expanded register file bitwidths and sizes. + # Hardware Implementations The fundamental principle of Simple-V is that it sits between Issue and