From: Andrew Stubbs <ams@codesourcery.com>
Date: Sat, 25 Jul 2020 14:02:52 +0000 (+0100)
Subject: amdgcn: Enable TImode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d0b2b33748014ee57973c1d7bc9fd7706bb3da9;p=gcc.git

amdgcn: Enable TImode

This enables types __int128 et al for move, add, subtract, and logical
operations.  At least shift, rotate, multiple, divide, and modulus are broken
so we can expect some test failures.

This is required now because libgomp no longer builds without __int128.

An additional patch will be required to unbreak the libgfortran build.

gcc/ChangeLog:

	* config/gcn/gcn.c (gcn_scalar_mode_supported_p): New function.
	(TARGET_SCALAR_MODE_SUPPORTED_P): New define.
---

diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index babecef7888..8b3c4544dd5 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -350,6 +350,19 @@ static const struct attribute_spec gcn_attribute_table[] = {
 /* }}}  */
 /* {{{ Registers and modes.  */
 
+/* Implement TARGET_SCALAR_MODE_SUPPORTED_P.  */
+
+bool
+gcn_scalar_mode_supported_p (scalar_mode mode)
+{
+  return (mode == BImode
+	  || mode == QImode
+	  || mode == HImode /* || mode == HFmode  */
+	  || mode == SImode || mode == SFmode
+	  || mode == DImode || mode == DFmode
+	  || mode == TImode);
+}
+
 /* Implement TARGET_CLASS_MAX_NREGS.
  
    Return the number of hard registers needed to hold a value of MODE in
@@ -6331,6 +6344,8 @@ gcn_dwarf_register_span (rtx rtl)
 #define TARGET_SECONDARY_RELOAD gcn_secondary_reload
 #undef  TARGET_SECTION_TYPE_FLAGS
 #define TARGET_SECTION_TYPE_FLAGS gcn_section_type_flags
+#undef  TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P gcn_scalar_mode_supported_p
 #undef  TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
   gcn_small_register_classes_for_mode_p