From: Florent Kermarrec Date: Thu, 22 Jan 2015 15:02:41 +0000 (+0100) Subject: change submodules/specials/clock_domains syntax X-Git-Tag: 24jan2021_ls180~2572^2~25 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d16a166c4720e2aac721f5f7dde3f81c66beae1;p=litex.git change submodules/specials/clock_domains syntax --- diff --git a/litesata/__init__.py b/litesata/__init__.py index d3f86a55..124e0281 100644 --- a/litesata/__init__.py +++ b/litesata/__init__.py @@ -12,10 +12,10 @@ class LiteSATA(Module, AutoCSR): self.phy = phy # core - self.core = LiteSATACore(self.phy, buffer_depth) + self.submodules.core = LiteSATACore(self.phy, buffer_depth) # frontend - self.crossbar = LiteSATACrossbar(self.core) + self.submodules.crossbar = LiteSATACrossbar(self.core) if with_bist: - self.bist = LiteSATABIST(self.crossbar, with_bist_csr) + self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr) diff --git a/litesata/common.py b/litesata/common.py index 18f5603c..d1653662 100644 --- a/litesata/common.py +++ b/litesata/common.py @@ -1,6 +1,7 @@ import math from migen.fhdl.std import * +from migen.fhdl.decorators import ModuleDecorator from migen.genlib.resetsync import * from migen.genlib.fsm import * from migen.genlib.record import * @@ -266,9 +267,9 @@ class Timeout(Module): self.sync += value.eq(value+1) self.comb += self.reached.eq(value == length) -class BufferizeEndpoints(Module): +class BufferizeEndpoints(ModuleDecorator): def __init__(self, submodule, *args): - self.submodule = submodule + ModuleDecorator.__init__(self, submodule) endpoints = get_endpoints(submodule) sinks = {} @@ -294,12 +295,6 @@ class BufferizeEndpoints(Module): self.comb += Record.connect(source, buf.d) setattr(self, name, buf.q) - def __getattr__(self, name): - return getattr(self.submodule, name) - - def __dir__(self): - return dir(self.submodule) - class EndpointPacketStatus(Module): def __init__(self, endpoint): self.start = Signal() @@ -334,14 +329,16 @@ class PacketBuffer(Module): def cmd_description(): layout = [("error", 1)] return EndpointDescription(layout) - self.cmd_fifo = cmd_fifo = SyncFIFO(cmd_description(), cmd_depth) + cmd_fifo = SyncFIFO(cmd_description(), cmd_depth) + self.submodules += cmd_fifo self.comb += [ cmd_fifo.sink.stb.eq(sink_status.done), cmd_fifo.sink.error.eq(sink.error) ] # data - self.data_fifo = data_fifo = SyncFIFO(description, data_depth, buffered=True) + data_fifo = SyncFIFO(description, data_depth, buffered=True) + self.submodules += data_fifo self.comb += [ Record.connect(self.sink, data_fifo.sink), data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack), @@ -350,6 +347,7 @@ class PacketBuffer(Module): # output packets self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", If(cmd_fifo.source.stb, NextState("SEEK_SOP") diff --git a/litesata/core/__init__.py b/litesata/core/__init__.py index ce7dc903..e318c5f2 100644 --- a/litesata/core/__init__.py +++ b/litesata/core/__init__.py @@ -5,7 +5,7 @@ from litesata.core.command import LiteSATACommand class LiteSATACore(Module): def __init__(self, phy, buffer_depth): - self.link = LiteSATALink(phy, buffer_depth) - self.transport = LiteSATATransport(self.link) - self.command = LiteSATACommand(self.transport) + self.submodules.link = LiteSATALink(phy, buffer_depth) + self.submodules.transport = LiteSATATransport(self.link) + self.submodules.command = LiteSATACommand(self.transport) self.sink, self.source = self.command.sink, self.command.source diff --git a/litesata/core/command/__init__.py b/litesata/core/command/__init__.py index 3a330839..0229befa 100644 --- a/litesata/core/command/__init__.py +++ b/litesata/core/command/__init__.py @@ -31,13 +31,15 @@ class LiteSATACommandTX(Module): transport.sink.data.eq(sink.data) ] - self.dwords_counter = dwords_counter = Counter(max=fis_max_dwords) + dwords_counter = Counter(max=fis_max_dwords) + self.submodules += dwords_counter is_write = Signal() is_read = Signal() is_identify = Signal() self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", sink.ack.eq(0), If(sink.stb & sink.sop, @@ -128,14 +130,15 @@ class LiteSATACommandRX(Module): is_identify = Signal() is_dma_activate = Signal() read_ndwords = Signal(max=sectors2dwords(2**16)) - self.dwords_counter = dwords_counter = Counter(max=sectors2dwords(2**16)) + dwords_counter = Counter(max=sectors2dwords(2**16)) + self.submodules += dwords_counter read_done = Signal() self.sync += \ If(from_tx.read, read_ndwords.eq(from_tx.count*sectors2dwords(1)-1) ) - self.comb += read_done.eq(self.dwords_counter.value == read_ndwords) + self.comb += read_done.eq(dwords_counter.value == read_ndwords) d2h_error = Signal() clr_d2h_error = Signal() @@ -158,8 +161,9 @@ class LiteSATACommandRX(Module): ) self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", - self.dwords_counter.reset.eq(1), + dwords_counter.reset.eq(1), transport.source.ack.eq(1), clr_d2h_error.eq(1), clr_read_error.eq(1), @@ -236,7 +240,7 @@ class LiteSATACommandRX(Module): source.data.eq(transport.source.data), transport.source.ack.eq(source.ack), If(source.stb & source.ack, - self.dwords_counter.ce.eq(~read_done), + dwords_counter.ce.eq(~read_done), If(source.eop, If(is_identify, NextState("IDLE") @@ -266,8 +270,8 @@ class LiteSATACommandRX(Module): class LiteSATACommand(Module): def __init__(self, transport): - self.tx = LiteSATACommandTX(transport) - self.rx = LiteSATACommandRX(transport) + self.submodules.tx = LiteSATACommandTX(transport) + self.submodules.rx = LiteSATACommandRX(transport) self.comb += [ self.rx.to_tx.connect(self.tx.from_rx), self.tx.to_rx.connect(self.rx.from_tx) diff --git a/litesata/core/link/__init__.py b/litesata/core/link/__init__.py index b6abd9df..2be40541 100644 --- a/litesata/core/link/__init__.py +++ b/litesata/core/link/__init__.py @@ -17,6 +17,7 @@ class LiteSATALinkTX(Module): ### self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm # insert CRC crc = LiteSATACRCInserter(link_description(32)) @@ -34,7 +35,8 @@ class LiteSATALinkTX(Module): # inserter CONT and scrambled data between # CONT and next primitive - self.cont = cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source") + cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source") + self.submodules += cont # datas / primitives mux insert = Signal(32) @@ -116,9 +118,11 @@ class LiteSATALinkRX(Module): ### self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm # CONT remover - self.cont = cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source") + cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source") + self.submodules += cont self.comb += Record.connect(phy.source, cont.sink) # datas / primitives detection @@ -130,10 +134,12 @@ class LiteSATALinkRX(Module): ) # descrambler - self.scrambler = scrambler = LiteSATAScrambler(link_description(32)) + scrambler = LiteSATAScrambler(link_description(32)) + self.submodules += scrambler # check CRC - self.crc = crc = LiteSATACRCChecker(link_description(32)) + crc = LiteSATACRCChecker(link_description(32)) + self.submodules += crc sop = Signal() eop = Signal() @@ -235,10 +241,10 @@ class LiteSATALinkRX(Module): class LiteSATALink(Module): def __init__(self, phy, buffer_depth): - self.tx_buffer = PacketBuffer(link_description(32), buffer_depth) - self.tx = LiteSATALinkTX(phy) - self.rx = LiteSATALinkRX(phy) - self.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4) + self.submodules.tx_buffer = PacketBuffer(link_description(32), buffer_depth) + self.submodules.tx = LiteSATALinkTX(phy) + self.submodules.rx = LiteSATALinkRX(phy) + self.submodules.rx_buffer = PacketBuffer(link_description(32), buffer_depth, almost_full=3*buffer_depth//4) self.comb += [ Record.connect(self.tx_buffer.source, self.tx.sink), Record.connect(self.rx.to_tx, self.tx.from_rx), diff --git a/litesata/core/link/cont.py b/litesata/core/link/cont.py index dff6a28f..0984374b 100644 --- a/litesata/core/link/cont.py +++ b/litesata/core/link/cont.py @@ -8,7 +8,8 @@ class LiteSATACONTInserter(Module): ### - self.counter = counter = Counter(max=4) + counter = Counter(max=4) + self.submodules += counter is_data = Signal() was_data = Signal() @@ -37,7 +38,8 @@ class LiteSATACONTInserter(Module): ) # scrambler - self.scrambler = scrambler = InsertReset(Scrambler()) + scrambler = InsertReset(Scrambler()) + self.submodules += scrambler # Datapath self.comb += [ diff --git a/litesata/core/link/crc.py b/litesata/core/link/crc.py index 89e4a13b..d73b047d 100644 --- a/litesata/core/link/crc.py +++ b/litesata/core/link/crc.py @@ -95,15 +95,16 @@ class LiteSATACRC(Module): ### - self.engine = CRCEngine(self.width, self.polynom) + engine = CRCEngine(self.width, self.polynom) + self.submodules += engine reg_i = Signal(self.width, reset=self.init) - self.sync += reg_i.eq(self.engine.next) + self.sync += reg_i.eq(engine.next) self.comb += [ - self.engine.d.eq(self.d), - self.engine.last.eq(reg_i), + engine.d.eq(self.d), + engine.last.eq(reg_i), self.value.eq(reg_i), - self.error.eq(self.engine.next != self.check) + self.error.eq(engine.next != self.check) ] class LiteSATACRCInserter(CRCInserter): diff --git a/litesata/core/link/scrambler.py b/litesata/core/link/scrambler.py index 4b5b9960..99ad98ce 100644 --- a/litesata/core/link/scrambler.py +++ b/litesata/core/link/scrambler.py @@ -72,9 +72,10 @@ class LiteSATAScrambler(Module): ### - self.scrambler = Scrambler() + scrambler = Scrambler() + self.submodules += scrambler self.comb += [ - self.scrambler.ce.eq(sink.stb & sink.ack), + scrambler.ce.eq(sink.stb & sink.ack), Record.connect(sink, source), - source.d.eq(sink.d ^ self.scrambler.value) + source.d.eq(sink.d ^ scrambler.value) ] diff --git a/litesata/core/transport/__init__.py b/litesata/core/transport/__init__.py index 7799a0d9..a066fb7c 100644 --- a/litesata/core/transport/__init__.py +++ b/litesata/core/transport/__init__.py @@ -30,7 +30,8 @@ class LiteSATATransportTX(Module): cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - self.counter = counter = Counter(max=cmd_ndwords+1) + counter = Counter(max=cmd_ndwords+1) + self.submodules += counter cmd_len = Signal(counter.width) cmd_with_data = Signal() @@ -46,6 +47,7 @@ class LiteSATATransportTX(Module): return test_type(name, sink.type) self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", sink.ack.eq(0), counter.reset.eq(1), @@ -131,7 +133,8 @@ class LiteSATATransportRX(Module): fis_pio_setup_d2h_cmd_len, fis_data_cmd_len) encoded_cmd = Signal(cmd_ndwords*32) - self.counter = counter = Counter(max=cmd_ndwords+1) + counter = Counter(max=cmd_ndwords+1) + self.submodules += counter cmd_len = Signal(counter.width) @@ -144,6 +147,7 @@ class LiteSATATransportRX(Module): return test_type(name, link.source.d[:8]) self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm data_sop = Signal() fis_type = Signal(8) @@ -248,6 +252,6 @@ class LiteSATATransportRX(Module): class LiteSATATransport(Module): def __init__(self, link): - self.tx = LiteSATATransportTX(link) - self.rx = LiteSATATransportRX(link) + self.submodules.tx = LiteSATATransportTX(link) + self.submodules.rx = LiteSATATransportRX(link) self.sink, self.source = self.tx.sink, self.rx.source diff --git a/litesata/frontend/arbiter.py b/litesata/frontend/arbiter.py index 73eafaa3..64bedf29 100644 --- a/litesata/frontend/arbiter.py +++ b/litesata/frontend/arbiter.py @@ -6,6 +6,7 @@ from migen.genlib.roundrobin import * class LiteSATAArbiter(Module): def __init__(self, users, master): self.rr = RoundRobin(len(users)) + self.submodules += self.rr self.grant = self.rr.grant cases = {} for i, slave in enumerate(users): diff --git a/litesata/frontend/bist.py b/litesata/frontend/bist.py index ae6d2999..aa1dbdcd 100644 --- a/litesata/frontend/bist.py +++ b/litesata/frontend/bist.py @@ -19,15 +19,18 @@ class LiteSATABISTGenerator(Module): source, sink = user_port.sink, user_port.source - self.counter = counter = Counter(bits_sign=32) + counter = Counter(bits_sign=32) + self.submodules += counter - self.scrambler = scrambler = InsertReset(Scrambler()) + scrambler = scrambler = InsertReset(Scrambler()) + self.submodules += scrambler self.comb += [ scrambler.reset.eq(counter.reset), scrambler.ce.eq(counter.ce) ] self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += fsm fsm.act("IDLE", self.done.eq(1), counter.reset.eq(1), @@ -79,21 +82,24 @@ class LiteSATABISTChecker(Module): source, sink = user_port.sink, user_port.source - self.counter = counter = Counter(bits_sign=32) - self.error_counter = Counter(self.errors, bits_sign=32) + counter = Counter(bits_sign=32) + error_counter = Counter(self.errors, bits_sign=32) + self.submodules += counter, error_counter - self.scrambler = scrambler = InsertReset(Scrambler()) + scrambler = InsertReset(Scrambler()) + self.submodules += scrambler self.comb += [ scrambler.reset.eq(counter.reset), scrambler.ce.eq(counter.ce) ] self.fsm = fsm = FSM(reset_state="IDLE") + self.submodules += self.fsm fsm.act("IDLE", self.done.eq(1), counter.reset.eq(1), If(self.start, - self.error_counter.reset.eq(1), + error_counter.reset.eq(1), NextState("SEND_CMD") ) ) @@ -128,7 +134,7 @@ class LiteSATABISTChecker(Module): If(sink.stb, counter.ce.eq(1), If(sink.data != expected_data, - self.error_counter.ce.eq(~sink.last) + error_counter.ce.eq(~sink.last) ), If(sink.eop, If(sink.last, @@ -156,7 +162,8 @@ class LiteSATABISTUnitCSR(Module, AutoCSR): ### - self.bist_unit = bist_unit + self.submodules += bist_unit + start = self._start.r & self._start.re done = self._done.status loops = self._loops.storage @@ -171,16 +178,17 @@ class LiteSATABISTUnitCSR(Module, AutoCSR): ] self.fsm = fsm = FSM(reset_state="IDLE") - self.loop_counter = Counter(bits_sign=8) + loop_counter = Counter(bits_sign=8) + self.submodules += fsm, loop_counter fsm.act("IDLE", self._done.status.eq(1), - self.loop_counter.reset.eq(1), + loop_counter.reset.eq(1), If(start, NextState("CHECK") ) ) fsm.act("CHECK", - If(self.loop_counter.value < loops, + If(loop_counter.value < loops, NextState("START") ).Else( NextState("IDLE") @@ -192,15 +200,16 @@ class LiteSATABISTUnitCSR(Module, AutoCSR): ) fsm.act("WAIT_DONE", If(bist_unit.done, - self.loop_counter.ce.eq(1), + loop_counter.ce.eq(1), NextState("CHECK") ) ) - self.cycles_counter = Counter(self._cycles.status) + cycles_counter = Counter(self._cycles.status) + self.submodules += cycles_counter self.sync += [ - self.cycles_counter.reset.eq(start), - self.cycles_counter.ce.eq(~fsm.ongoing("IDLE")) + cycles_counter.reset.eq(start), + cycles_counter.ce.eq(~fsm.ongoing("IDLE")) ] class LiteSATABISTIdentify(Module): @@ -208,8 +217,9 @@ class LiteSATABISTIdentify(Module): self.start = Signal() self.done = Signal() - self.fifo = fifo = SyncFIFO([("data", 32)], 512, buffered=True) - self.source = self.fifo.source + fifo = SyncFIFO([("data", 32)], 512, buffered=True) + self.submodules += fifo + self.source = fifo.source ### @@ -259,7 +269,7 @@ class LiteSATABISTIdentifyCSR(Module, AutoCSR): ### - self.bist_identify = bist_identify + self.submodules += bist_identify self.comb += [ bist_identify.start.eq(self._start.r & self._start.re), self._done.status.eq(bist_identify.done), @@ -275,10 +285,7 @@ class LiteSATABIST(Module, AutoCSR): checker = LiteSATABISTChecker(crossbar.get_port()) identify = LiteSATABISTIdentify(crossbar.get_port()) if with_csr: - self.generator = LiteSATABISTUnitCSR(generator) - self.checker = LiteSATABISTUnitCSR(checker) - self.identify = LiteSATABISTIdentifyCSR(identify) - else: - self.generator = generator - self.checker = checker - self.identify = identify + generator = LiteSATABISTUnitCSR(generator) + checker = LiteSATABISTUnitCSR(checker) + identify = LiteSATABISTIdentifyCSR(identify) + self.submodules += generator, checker, identify diff --git a/litesata/frontend/crossbar.py b/litesata/frontend/crossbar.py index d916209c..22170449 100644 --- a/litesata/frontend/crossbar.py +++ b/litesata/frontend/crossbar.py @@ -23,4 +23,5 @@ class LiteSATACrossbar(Module): return ports def do_finalize(self): - self.arbiter = LiteSATAArbiter(self.users, self.master) + arbiter = LiteSATAArbiter(self.users, self.master) + self.submodules += arbiter \ No newline at end of file diff --git a/litesata/phy/__init__.py b/litesata/phy/__init__.py index 5978250d..7af74b2d 100644 --- a/litesata/phy/__init__.py +++ b/litesata/phy/__init__.py @@ -10,15 +10,15 @@ class LiteSATAPHY(Module): if device[:3] == "xc7": # Kintex 7 from litesata.phy.k7.trx import K7LiteSATAPHYTRX from litesata.phy.k7.crg import K7LiteSATAPHYCRG - self.trx = K7LiteSATAPHYTRX(pads, revision) - self.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq) + self.submodules.trx = K7LiteSATAPHYTRX(pads, revision) + self.submodules.crg = K7LiteSATAPHYCRG(pads, self.trx, revision, clk_freq) else: msg = "Device" + device + "not (yet) supported." raise NotImplementedError(msg) # Control - self.ctrl = LiteSATAPHYCtrl(self.trx, self.crg, clk_freq) + self.submodules.ctrl = LiteSATAPHYCtrl(self.trx, self.crg, clk_freq) # Datapath - self.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl) + self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl) self.sink, self.source = self.datapath.sink, self.datapath.source diff --git a/litesata/phy/ctrl.py b/litesata/phy/ctrl.py index 23d64085..fc48a65c 100644 --- a/litesata/phy/ctrl.py +++ b/litesata/phy/ctrl.py @@ -25,6 +25,7 @@ class LiteSATAPHYCtrl(Module): non_align_cnt = Signal(4) self.fsm = fsm = FSM(reset_state="RESET") + self.submodules += fsm fsm.act("RESET", trx.tx_idle.eq(1), retry_timeout.reset.eq(1), @@ -128,10 +129,11 @@ class LiteSATAPHYCtrl(Module): self.ready.eq(1), ) - self.reset_timeout = Timeout(clk_freq//16) + reset_timeout = Timeout(clk_freq//16) + self.submodules += reset_timeout self.comb += [ - self.reset_timeout.ce.eq(~self.ready), - self.need_reset.eq(self.reset_timeout.reached) + reset_timeout.ce.eq(~self.ready), + self.need_reset.eq(reset_timeout.reached) ] self.comb += \ diff --git a/litesata/phy/datapath.py b/litesata/phy/datapath.py index c47e7529..60f55442 100644 --- a/litesata/phy/datapath.py +++ b/litesata/phy/datapath.py @@ -2,8 +2,8 @@ from litesata.common import * class LiteSATAPHYDatapathRX(Module): def __init__(self): - self.sink = Sink(phy_description(16)) - self.source = Source(phy_description(32)) + self.sink = sink = Sink(phy_description(16)) + self.source = source = Source(phy_description(32)) ### @@ -12,26 +12,27 @@ class LiteSATAPHYDatapathRX(Module): last_charisk = Signal(2) last_data = Signal(16) self.sync.sata_rx += \ - If(self.sink.stb & self.sink.ack, - If(self.sink.charisk != 0, - byte_alignment.eq(self.sink.charisk[1]) + If(sink.stb & sink.ack, + If(sink.charisk != 0, + byte_alignment.eq(sink.charisk[1]) ), - last_charisk.eq(self.sink.charisk), - last_data.eq(self.sink.data) + last_charisk.eq(sink.charisk), + last_data.eq(sink.data) ) converter = Converter(phy_description(16), phy_description(32), reverse=False) - self.converter = InsertReset(RenameClockDomains(converter, "sata_rx")) + converter = InsertReset(RenameClockDomains(converter, "sata_rx")) + self.submodules += converter self.comb += [ - self.converter.sink.stb.eq(self.sink.stb), + converter.sink.stb.eq(sink.stb), If(byte_alignment, - self.converter.sink.charisk.eq(Cat(last_charisk[1], self.sink.charisk[0])), - self.converter.sink.data.eq(Cat(last_data[8:], self.sink.data[:8])) + converter.sink.charisk.eq(Cat(last_charisk[1], sink.charisk[0])), + converter.sink.data.eq(Cat(last_data[8:], sink.data[:8])) ).Else( - self.converter.sink.charisk.eq(self.sink.charisk), - self.converter.sink.data.eq(self.sink.data) + converter.sink.charisk.eq(sink.charisk), + converter.sink.data.eq(sink.data) ), - self.sink.ack.eq(self.converter.sink.ack), - self.converter.reset.eq(self.converter.source.charisk[2:] != 0) + sink.ack.eq(converter.sink.ack), + converter.reset.eq(converter.source.charisk[2:] != 0) ] # clock domain crossing @@ -42,16 +43,17 @@ class LiteSATAPHYDatapathRX(Module): # due to the convertion ratio of 2, sys_clk need to be > sata_rx/2 # source destination is always able to accept data (ack always 1) fifo = AsyncFIFO(phy_description(32), 4) - self.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"}) + fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"}) + self.submodules += fifo self.comb += [ - Record.connect(self.converter.source, fifo.sink), - Record.connect(fifo.source, self.source) + Record.connect(converter.source, fifo.sink), + Record.connect(fifo.source, source) ] class LiteSATAPHYDatapathTX(Module): def __init__(self): - self.sink = Sink(phy_description(32)) - self.source = Source(phy_description(16)) + self.sink = sink = Sink(phy_description(32)) + self.source = source = Source(phy_description(16)) ### @@ -62,15 +64,17 @@ class LiteSATAPHYDatapathTX(Module): # requirements: # source destination is always able to accept data (ack always 1) fifo = AsyncFIFO(phy_description(32), 4) - self.fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"}) - self.comb += Record.connect(self.sink, fifo.sink) + fifo = RenameClockDomains(fifo, {"write": "sys", "read": "sata_tx"}) + self.submodules += fifo + self.comb += Record.connect(sink, fifo.sink) # width convertion (32 to 16) converter = Converter(phy_description(32), phy_description(16), reverse=False) - self.converter = RenameClockDomains(converter, "sata_tx") + converter = RenameClockDomains(converter, "sata_tx") + self.submodules += converter self.comb += [ - Record.connect(self.fifo.source, self.converter.sink), - Record.connect(self.converter.source, self.source) + Record.connect(fifo.source, converter.sink), + Record.connect(converter.source, source) ] class LiteSATAPHYAlignInserter(Module): @@ -125,33 +129,35 @@ class LiteSATAPHYAlignRemover(Module): class LiteSATAPHYDatapath(Module): def __init__(self, trx, ctrl): - self.sink = Sink(phy_description(32)) - self.source = Source(phy_description(32)) + self.sink = sink = Sink(phy_description(32)) + self.source = source = Source(phy_description(32)) ### # TX path - self.align_inserter = LiteSATAPHYAlignInserter(ctrl) - self.mux = Multiplexer(phy_description(32), 2) - self.tx = LiteSATAPHYDatapathTX() + align_inserter = LiteSATAPHYAlignInserter(ctrl) + mux = Multiplexer(phy_description(32), 2) + tx = LiteSATAPHYDatapathTX() + self.submodules += align_inserter, mux, tx self.comb += [ - self.mux.sel.eq(ctrl.ready), - Record.connect(self.sink, self.align_inserter.sink), - Record.connect(ctrl.source, self.mux.sink0), - Record.connect(self.align_inserter.source, self.mux.sink1), - Record.connect(self.mux.source, self.tx.sink), - Record.connect(self.tx.source, trx.sink) + mux.sel.eq(ctrl.ready), + Record.connect(sink, align_inserter.sink), + Record.connect(ctrl.source, mux.sink0), + Record.connect(align_inserter.source, mux.sink1), + Record.connect(mux.source, tx.sink), + Record.connect(tx.source, trx.sink) ] # RX path - self.rx = LiteSATAPHYDatapathRX() - self.demux = Demultiplexer(phy_description(32), 2) - self.align_remover = LiteSATAPHYAlignRemover() + rx = LiteSATAPHYDatapathRX() + demux = Demultiplexer(phy_description(32), 2) + align_remover = LiteSATAPHYAlignRemover() + self.submodules += rx, demux, align_remover self.comb += [ - self.demux.sel.eq(ctrl.ready), - Record.connect(trx.source, self.rx.sink), - Record.connect(self.rx.source, self.demux.sink), - Record.connect(self.demux.source0, ctrl.sink), - Record.connect(self.demux.source1, self.align_remover.sink), - Record.connect(self.align_remover.source, self.source) + demux.sel.eq(ctrl.ready), + Record.connect(trx.source, rx.sink), + Record.connect(rx.source, demux.sink), + Record.connect(demux.source0, ctrl.sink), + Record.connect(demux.source1, align_remover.sink), + Record.connect(align_remover.source, source) ] diff --git a/litesata/phy/k7/crg.py b/litesata/phy/k7/crg.py index c3267c6c..9830b45b 100644 --- a/litesata/phy/k7/crg.py +++ b/litesata/phy/k7/crg.py @@ -5,8 +5,8 @@ class K7LiteSATAPHYCRG(Module): self.reset = Signal() self.ready = Signal() - self.cd_sata_tx = ClockDomain() - self.cd_sata_rx = ClockDomain() + self.clock_domains.cd_sata_tx = ClockDomain() + self.clock_domains.cd_sata_rx = ClockDomain() # CPLL # (SATA3) 150MHz / VCO @ 3GHz / Line rate @ 6Gbps diff --git a/litesata/test/bist_tb.py b/litesata/test/bist_tb.py index e96b3c03..483ffb7d 100644 --- a/litesata/test/bist_tb.py +++ b/litesata/test/bist_tb.py @@ -7,13 +7,13 @@ from litesata.test.common import * class TB(Module): def __init__(self): - self.hdd = HDD( + self.submodules.hdd = HDD( link_debug=False, link_random_level=0, transport_debug=False, transport_loopback=False, hdd_debug=True) - self.controller = LiteSATA(self.hdd.phy) - self.generator = LiteSATABISTGenerator(self.controller.crossbar.get_port()) - self.checker = LiteSATABISTChecker(self.controller.crossbar.get_port()) + self.submodules.controller = LiteSATA(self.hdd.phy) + self.submodules.generator = LiteSATABISTGenerator(self.controller.crossbar.get_port()) + self.submodules.checker = LiteSATABISTChecker(self.controller.crossbar.get_port()) def gen_simulation(self, selfp): hdd = self.hdd diff --git a/litesata/test/command_tb.py b/litesata/test/command_tb.py index 566902fd..2bcc820e 100644 --- a/litesata/test/command_tb.py +++ b/litesata/test/command_tb.py @@ -53,19 +53,19 @@ class CommandLogger(PacketLogger): class TB(Module): def __init__(self): - self.hdd = HDD( + self.submodules.hdd = HDD( link_debug=False, link_random_level=50, transport_debug=False, transport_loopback=False, hdd_debug=True) - self.core = LiteSATACore(self.hdd.phy, buffer_depth=512) + self.submodules.core = LiteSATACore(self.hdd.phy, buffer_depth=512) - self.streamer = CommandStreamer() - self.streamer_randomizer = Randomizer(command_tx_description(32), level=50) + self.submodules.streamer = CommandStreamer() + self.submodules.streamer_randomizer = Randomizer(command_tx_description(32), level=50) - self.logger = CommandLogger() - self.logger_randomizer = Randomizer(command_rx_description(32), level=50) + self.submodules.logger = CommandLogger() + self.submodules.logger_randomizer = Randomizer(command_rx_description(32), level=50) - self.pipeline = Pipeline( + self.submodules.pipeline = Pipeline( self.streamer, self.streamer_randomizer, self.core, diff --git a/litesata/test/cont_tb.py b/litesata/test/cont_tb.py index bbd69011..cdbb9bf2 100644 --- a/litesata/test/cont_tb.py +++ b/litesata/test/cont_tb.py @@ -32,14 +32,14 @@ class ContLogger(PacketLogger): class TB(Module): def __init__(self): - self.streamer = ContStreamer() - self.streamer_randomizer = Randomizer(phy_description(32), level=50) - self.inserter = LiteSATACONTInserter(phy_description(32)) - self.remover = LiteSATACONTRemover(phy_description(32)) - self.logger_randomizer = Randomizer(phy_description(32), level=50) - self.logger = ContLogger() + self.submodules.streamer = ContStreamer() + self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=50) + self.submodules.inserter = LiteSATACONTInserter(phy_description(32)) + self.submodules.remover = LiteSATACONTRemover(phy_description(32)) + self.submodules.logger_randomizer = Randomizer(phy_description(32), level=50) + self.submodules.logger = ContLogger() - self.pipeline = Pipeline( + self.submodules.pipeline = Pipeline( self.streamer, self.streamer_randomizer, self.inserter, diff --git a/litesata/test/crc_tb.py b/litesata/test/crc_tb.py index a36ec839..3799f755 100644 --- a/litesata/test/crc_tb.py +++ b/litesata/test/crc_tb.py @@ -7,7 +7,7 @@ from litesata.test.common import * class TB(Module): def __init__(self, length, random): - self.crc = LiteSATACRC() + self.submodules.crc = LiteSATACRC() self.length = length self.random = random diff --git a/litesata/test/hdd.py b/litesata/test/hdd.py index 6e897f8e..cab36265 100644 --- a/litesata/test/hdd.py +++ b/litesata/test/hdd.py @@ -56,8 +56,8 @@ class PHYSink(Module): class PHYLayer(Module): def __init__(self): - self.rx = PHYSink() - self.tx = PHYSource() + self.submodules.rx = PHYSink() + self.submodules.tx = PHYSource() self.source = self.tx.source self.sink = self.rx.sink @@ -439,10 +439,10 @@ class HDD(Module): hdd_debug=False, ): ### - self.phy = PHYLayer() - self.link = LinkLayer(self.phy, link_debug, link_random_level) - self.transport = TransportLayer(self.link, transport_debug, transport_loopback) - self.command = CommandLayer(self.transport) + self.submodules.phy = PHYLayer() + self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level) + self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback) + self.submodules.command = CommandLayer(self.transport) self.command.set_hdd(self) diff --git a/litesata/test/link_tb.py b/litesata/test/link_tb.py index 17abe2c8..def4e14d 100644 --- a/litesata/test/link_tb.py +++ b/litesata/test/link_tb.py @@ -14,18 +14,18 @@ class LinkLogger(PacketLogger): class TB(Module): def __init__(self): - self.hdd = HDD( + self.submodules.hdd = HDD( link_debug=False, link_random_level=50, transport_debug=False, transport_loopback=True) - self.link = InsertReset(LiteSATALink(self.hdd.phy, buffer_depth=512)) + self.submodules.link = InsertReset(LiteSATALink(self.hdd.phy, buffer_depth=512)) - self.streamer = LinkStreamer() - self.streamer_randomizer = Randomizer(link_description(32), level=50) + self.submodules.streamer = LinkStreamer() + self.submodules.streamer_randomizer = Randomizer(link_description(32), level=50) - self.logger_randomizer = Randomizer(link_description(32), level=50) - self.logger = LinkLogger() + self.submodules.logger_randomizer = Randomizer(link_description(32), level=50) + self.submodules.logger = LinkLogger() - self.pipeline = Pipeline( + self.submodules.pipeline = Pipeline( self.streamer, self.streamer_randomizer, self.link, diff --git a/litesata/test/phy_datapath_tb.py b/litesata/test/phy_datapath_tb.py index 71071035..a1c2d4c5 100644 --- a/litesata/test/phy_datapath_tb.py +++ b/litesata/test/phy_datapath_tb.py @@ -1,5 +1,5 @@ from litesata.common import * -from litesata.phy.datapath import liteSATAPHYDatapath +from litesata.phy.datapath import LiteSATAPHYDatapath from litesata.test.common import * @@ -45,8 +45,8 @@ class CTRL(Module): class TB(Module): def __init__(self): # use sys_clk for each clock_domain - self.cd_sata_rx = ClockDomain() - self.cd_sata_tx = ClockDomain() + self.clock_domains.cd_sata_rx = ClockDomain() + self.clock_domains.cd_sata_tx = ClockDomain() self.comb += [ self.cd_sata_rx.clk.eq(ClockSignal()), self.cd_sata_rx.rst.eq(ResetSignal()), @@ -54,15 +54,15 @@ class TB(Module): self.cd_sata_tx.rst.eq(ResetSignal()), ] - self.streamer = DataStreamer() - self.streamer_randomizer = Randomizer(phy_description(32), level=10) - self.trx = TRX() - self.ctrl = CTRL() - self.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl) - self.logger_randomizer = Randomizer(phy_description(32), level=10) - self.logger = DataLogger() + self.submodules.streamer = DataStreamer() + self.submodules.streamer_randomizer = Randomizer(phy_description(32), level=10) + self.submodules.trx = TRX() + self.submodules.ctrl = CTRL() + self.submodules.datapath = LiteSATAPHYDatapath(self.trx, self.ctrl) + self.submodules.logger_randomizer = Randomizer(phy_description(32), level=10) + self.submodules.logger = DataLogger() - self.pipeline = Pipeline( + self.submodules.pipeline = Pipeline( self.streamer, self.streamer_randomizer, self.datapath, diff --git a/litesata/test/scrambler_tb.py b/litesata/test/scrambler_tb.py index bf29e50c..11d626b1 100644 --- a/litesata/test/scrambler_tb.py +++ b/litesata/test/scrambler_tb.py @@ -7,7 +7,7 @@ from litesata.test.common import * class TB(Module): def __init__(self, length): - self.scrambler = InsertReset(Scrambler()) + self.submodules.scrambler = InsertReset(Scrambler()) self.length = length def get_c_values(self, length): diff --git a/targets/bist.py b/targets/bist.py index f7ff733f..a62fdf00 100644 --- a/targets/bist.py +++ b/targets/bist.py @@ -18,7 +18,7 @@ from litesata import LiteSATA class _CRG(Module): def __init__(self, platform): - self.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() self.reset = Signal() clk200 = platform.request("clk200") @@ -63,16 +63,16 @@ class GenSoC(Module): cpu_type = None def __init__(self, platform, clk_freq): # UART <--> Wishbone bridge - self.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600) + self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600) # CSR bridge 0x00000000 (shadow @0x00000000) - self.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) + self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width)) self._wb_masters = [self.uart2wb.wishbone] self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)] self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory) # CSR - self.identifier = identifier.Identifier(0, int(clk_freq), 0) + self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0) def add_cpu_memory_region(self, name, origin, length): self.cpu_memory_regions.append((name, origin, length)) @@ -82,14 +82,14 @@ class GenSoC(Module): def do_finalize(self): # Wishbone - self.wishbonecon = wishbone.InterconnectShared(self._wb_masters, + self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves, register=True) # CSR - self.csrbankarray = csrgen.BankArray(self, + self.submodules.csrbankarray = csrgen.BankArray(self, lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override], data_width=self.csr_data_width) - self.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) + self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: @@ -136,15 +136,15 @@ class BISTSoC(GenSoC, AutoCSR): def __init__(self, platform, export_mila=False): clk_freq = 166*1000000 GenSoC.__init__(self, platform, clk_freq) - self.crg = _CRG(platform) + self.submodules.crg = _CRG(platform) # SATA PHY/Core/Frontend - self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) + self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME - self.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True) + self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True) # Status Leds - self.leds = BISTLeds(platform, self.sata_phy) + self.submodules.leds = BISTLeds(platform, self.sata_phy) class BISTSoCDevel(BISTSoC, AutoCSR): csr_map = { @@ -198,7 +198,7 @@ class BISTSoCDevel(BISTSoC, AutoCSR): self.sata_core_command_tx_fsm_state, ) - self.mila = MiLa(depth=2048, dat=Cat(*debug)) + self.submodules.mila = MiLa(depth=2048, dat=Cat(*debug)) self.mila.add_port(Term) if export_mila: mila_filename = os.path.join("test", "mila.csv") diff --git a/targets/core.py b/targets/core.py index 3036a542..b876e243 100644 --- a/targets/core.py +++ b/targets/core.py @@ -6,7 +6,7 @@ from litesata import LiteSATA class _CRG(Module): def __init__(self, platform): - self.cd_sys = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() class LiteSATACore(Module): default_platform = "verilog_backend" @@ -16,15 +16,14 @@ class LiteSATACore(Module): self.crg = _CRG(platform) # SATA PHY/Core/Frontend - self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) - self.sata = LiteSATA(self.sata_phy) + self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq) + self.submodules.sata = LiteSATA(self.sata_phy) # Get user ports from crossbar self.user_ports = self.sata.crossbar.get_ports(4) def get_ios(self): - # clock / reset - ios = {self.crg.cd_sys.clk, self.crg.cd_sys.rst} + ios = set() # Transceiver for e in dir(self.sata_phy.pads):