From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 03:31:56 +0000 (-0700)
Subject: Merge branch 'master' into xaig
X-Git-Tag: working-ls180~1237^2~57
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d18c256f0d6fee25fe7a55ed7d882c478465b09;p=yosys.git

Merge branch 'master' into xaig
---

8d18c256f0d6fee25fe7a55ed7d882c478465b09
diff --cc CHANGELOG
index 192fc5a8d,128f6c6ff..0636e6bad
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -16,14 -16,11 +16,16 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
 +    - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
+     - Added "muxcover -mux{4,8,16}=<cost>"
+     - Added "muxcover -dmux=<cost>"
+     - Added "muxcover -nopartial"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
-     - Extended "muxcover -mux{4,8,16}=<cost>"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB