From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 21:34:27 +0000 (-0700)
Subject: opt_expr: remove redundant
X-Git-Tag: working-ls180~709^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606;p=yosys.git

opt_expr: remove redundant
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c818fefc5..723830aa0 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -682,9 +682,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
 				RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
 
-				if (sig_ci.wire || sig_bi.wire)
-					goto next_cell;
-
 				bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
 
 				// If not a subtraction, yet there is a carry or B is inverted