From: lkcl <lkcl@web>
Date: Sun, 28 Nov 2021 21:36:03 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3349
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d2e54ce6b3a23b2aecf1f31533c043e36ae7326;p=libreriscv.git

---

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 99e59a397..3588d4670 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -204,3 +204,16 @@ Here is a function that defines a UART Resource:
       io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
       io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
       return Resource.family(*args, default_name="uart", ios=io)
+
+It would typically be part of a larger function that defines, for either
+an FPGA or an ASIC, a full array of IO Connections:
+
+    def create_resources(pinset):
+       resources = []
+       resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
+       # add clock and reset
+       clk = Resource("clk", 0, Pins("sys_clk", dir="i"))
+       rst = Resource("rst", 0, Pins("sys_rst", dir="i"))
+       resources.append(clk)
+       resources.append(rst)
+       return resources