From: Nikos Nikoleris <nikos.nikoleris@arm.com>
Date: Mon, 25 Sep 2017 15:43:37 +0000 (+0100)
Subject: arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1
X-Git-Tag: v19.0.0.0~2579
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d43922;p=gem5.git

arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1

A program running in EL0 is allowed to execute CMOs when the UCI bit
in SCTLR is set. The execution of dc ivac, however, would fault
uncoditionally when executed from EL0. This change aligns the
permission checks for dc ivac with the rest of the CMOs.

Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5058
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 20861480b..d31c84ca6 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1066,7 +1066,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
     // MISCREG_IC_IALLU
     bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
     // MISCREG_DC_IVAC_Xt
-    bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
+    bitset<NUM_MISCREG_INFOS>(string("10101010101010000101")),
     // MISCREG_DC_ISW_Xt
     bitset<NUM_MISCREG_INFOS>(string("10101010100000000101")),
     // MISCREG_AT_S1E1R_Xt
@@ -2149,7 +2149,8 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
         if (el == EL0 && !sctlr.dze)
             return false;
     }
-    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
+    if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
+        reg == MISCREG_DC_IVAC_Xt) {
         SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
         if (el == EL0 && !sctlr.uci)
             return false;