From: Luke Kenneth Casson Leighton Date: Sat, 16 Feb 2019 12:10:49 +0000 (+0000) Subject: first initial success with div algorithm X-Git-Tag: ls180-24jan2020~1942 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d492f5eec29ba2910f4d250dca70fa08f4170df;p=ieee754fpu.git first initial success with div algorithm --- diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py index e6f68b84..ddd9f671 100644 --- a/src/add/nmigen_div_experiment.py +++ b/src/add/nmigen_div_experiment.py @@ -2,7 +2,7 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Const +from nmigen import Module, Signal, Const, Cat from nmigen.cli import main, verilog from fpbase import FPNum, FPOp, Overflow, FPBase @@ -46,7 +46,7 @@ class FPDIV(FPBase): b = FPNum(self.width, 24) z = FPNum(self.width, 24) - div = Div(50) + div = Div(51) of = Overflow() @@ -147,7 +147,7 @@ class FPDIV(FPBase): m.next = "divide_2" m.d.sync += [ div.quotient.eq(div.quotient << 1), - div.remainder.eq(Cat(dividend[0], div.remainder[2:])), + div.remainder.eq(Cat(div.dividend[50], div.remainder[0:])), div.dividend.eq(div.dividend << 1), ] @@ -160,7 +160,7 @@ class FPDIV(FPBase): div.quotient[0].eq(1), div.remainder.eq(div.remainder - div.divisor), ] - with m.If(count == div.width-1): + with m.If(div.count == div.width-2): m.next = "divide_3" with m.Else(): m.next = "divide_1" @@ -177,7 +177,7 @@ class FPDIV(FPBase): z.m.eq(div.quotient[3:27]), of.guard.eq(div.quotient[2]), of.round_bit.eq(div.quotient[1]), - of.sticky.eq(div.quotient[0] | div.remainder != 0) + of.sticky.eq(div.quotient[0] | (div.remainder != 0)) ] # ****** diff --git a/src/add/test_div.py b/src/add/test_div.py index 513980b4..2945f5be 100644 --- a/src/add/test_div.py +++ b/src/add/test_div.py @@ -47,8 +47,10 @@ def check_case(dut, a, b, z): def testbench(dut): yield from check_case(dut, 0x40000000, 0x3F800000, 0x40000000) + yield from check_case(dut, 0x3F800000, 0x40000000, 0x3F000000) + yield from check_case(dut, 0x3F800000, 0x40400000, 0x3EAAAAAB) if __name__ == '__main__': dut = FPDIV(width=32) - run_simulation(dut, testbench(dut), vcd_name="test_add.vcd") + run_simulation(dut, testbench(dut), vcd_name="test_div.vcd")