From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 25 Apr 2021 14:18:29 +0000 (-0300)
Subject: Improve debug information on mtcrf test case
X-Git-Tag: 0.0.3~107
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d4f847645a90a04a55de0757f5db00aa1d31902;p=openpower-isa.git

Improve debug information on mtcrf test case
---

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index ce934609..710fc6c0 100644
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -314,7 +314,7 @@ class DecoderTestCase(FHDLTestCase):
             print("cr", sim.cr)
             expected = (7-i)
             # check CR[0]/1/2/3 as well
-            print("cr%d", sim.crl[i])
+            print("cr%d" % i, sim.crl[i].asint(True))
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
             # check CR itself
             self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))