From: Peter Bergner <bergner@vnet.ibm.com>
Date: Tue, 13 Feb 2018 23:05:59 +0000 (-0600)
Subject: re PR target/84279 (powerpc64le ICE on cvc4)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d61eea7cc082271071d167541a106e17835c7d8;p=gcc.git

re PR target/84279 (powerpc64le ICE on cvc4)

gcc/
	PR target/84279
	* config/rs6000/rs6000.c (mem_operand_gpr): Disallow altivec addresses.

gcc/testsuite/
	PR target/84279
	* g++.dg/pr84279.C: New test.

From-SVN: r257647
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 41ded5f7ef1..3ddfff6564b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-02-13  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR target/84279
+	* config/rs6000/rs6000.c (mem_operand_gpr): Disallow altivec addresses.
+
 2018-02-13  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	PR rtl-optimization/84169
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6a6801aad9b..ddfc10666a3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -8220,6 +8220,12 @@ mem_operand_gpr (rtx op, machine_mode mode)
   int extra;
   rtx addr = XEXP (op, 0);
 
+  /* Don't allow altivec type addresses like (mem (and (plus ...))).
+     See PR target/84279.  */
+
+  if (GET_CODE (addr) == AND)
+    return false;
+
   op = address_offset (addr);
   if (op == NULL_RTX)
     return true;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 034931bad9b..eec738ef3fd 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-02-13  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR target/84279
+	* g++.dg/pr84279.C: New test.
+
 2018-02-13  Segher Boessenkool  <segher@kernel.crashing.org>
 
 	PR rtl-optimization/84169
diff --git a/gcc/testsuite/g++.dg/pr84279.C b/gcc/testsuite/g++.dg/pr84279.C
new file mode 100644
index 00000000000..a88d3fb8470
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr84279.C
@@ -0,0 +1,35 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-O3 -mcpu=power8 -g -fPIC -fvisibility=hidden -fstack-protector-strong" } */
+
+template <typename, typename T> struct E { T e; };
+struct J {
+  unsigned k, l;
+  J (unsigned x, unsigned y) : k(x), l(y) {}
+};
+typedef struct A {
+  J n, p;
+  A ();
+  A (J x, J y) : n(x), p(y) {}
+} *S;
+S t;
+struct B {
+  struct C {
+    S q, r;
+    int u, v;
+    bool m1 (S, A &);
+    J m2 () const;
+    J m3 () const;
+    A m4 () const;
+  };
+  typedef E<unsigned, S> D;
+  void m5 (D *);
+  void m6 (unsigned, A);
+};
+bool B::C::m1 (S, A &x) { bool o; x = m4 (); return o; }
+J B::C::m2 () const { unsigned g (u == 0); unsigned h (v); return J (g, h); }
+J B::C::m3 () const { unsigned g (q != t); unsigned h (r != t); return J (g, h); }
+A B::C::m4 () const { return A (m2 (), m3 ()); }
+void B::m5 (D *c) { unsigned x; C ar; A am; if (ar.m1 (c->e, am)) m6 (x, am); }