From: lkcl <lkcl@web>
Date: Sun, 23 Apr 2023 12:52:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d63d1ebf18c51fbcf395f4b933c754e8eb1cfe5;p=libreriscv.git

---

diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index 74d4b0e12..e6e9d17b3 100644
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -147,8 +147,9 @@ to statically detect and potentially express.
 independent of each other (no Register *or Memory* Hazards).
 
 Elements are considered to be in the same source batch if they have
-the same value of `FLOOR(srcstep/hphint)`. Likewise in the same destination batch.
-Three key observations here:
+the same value of `FLOOR(srcstep/hphint)`. Likewise in the same destination batch
+for the same value `FLOOR(dststep/hphint)`.
+Four key observations here:
 
 1. predication is **not** involved here.  the number of actual elements
 involved is considered *before* predicate masks are applied.
@@ -156,6 +157,10 @@ involved is considered *before* predicate masks are applied.
 batches
 3. batch evaluation is done *before* REMAP, making Hazard elimination easier
    for Multi-Issue systems.
+4. `hphint` is *not* limited to power-of-two. Hardware implementors may choose
+   a lower parallelism hint up to `hphint` and may find power-of-two more
+   convenient. Actual parallelism (Dependency Hazard relaxation) must **never**
+   exceed `hphint`.
 
 *Hardware Architect note: each element within the same group may be treated as
 100% independent from any other element within that group, and therefore