From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 14:40:20 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~549
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d7a434ea36fda6edbdfaa282a0f22eca4673323;p=libreriscv.git

---

diff --git a/openpower/sv/mv.vec.mdwn b/openpower/sv/mv.vec.mdwn
index 28d6e8ec4..ac7301c6f 100644
--- a/openpower/sv/mv.vec.mdwn
+++ b/openpower/sv/mv.vec.mdwn
@@ -4,6 +4,8 @@ In the SIMD VSX set, section 6.8.1 and 6.8.2 p254 of v3.0B has a series of pack
 
 See <https://bugs.libre-soc.org/show_bug.cgi?id=230#c30>
 
+Note that some of these may be covered by [[remap] which is described in [[sv/propagation]]
+
 # move to/from vec2/3/4
 
 Basic idea: mv operations where either the src or dest is specifically marked as having SUBVL apply to it, but, crucially, the *other* argument does *not*. Note that this is highly unusual in SimpleV, which normally only allows SUBVL to be applied uniformly across all dest and all src.