From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 22:19:10 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig_arrival
X-Git-Tag: working-ls180~1075^2^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d820a9884c0a58ee7817a2052d8b915578a7ba7;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig_arrival
---

8d820a9884c0a58ee7817a2052d8b915578a7ba7
diff --cc techlibs/xilinx/cells_sim.v
index e2ec4e525,e12b77c02..b4657daca
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -213,13 -236,7 +228,15 @@@ endmodul
  
  `endif
  
 -module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 +// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
 +
 +module FDRE (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, R
++  (* clkbuf_sink *)
++  input C, 
++  input CE, D, R
 +);
    parameter [0:0] INIT = 1'b0;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_D_INVERTED = 1'b0;
@@@ -231,11 -248,7 +248,13 @@@
    endcase endgenerate
  endmodule
  
 -module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 +module FDSE (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, S
++  (* clkbuf_sink *)
++  input C,
++  input CE, D, S
 +);
    parameter [0:0] INIT = 1'b1;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_D_INVERTED = 1'b0;
@@@ -247,11 -260,7 +266,13 @@@
    endcase endgenerate
  endmodule
  
 -module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 +module FDCE (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, CLR
++  (* clkbuf_sink *) 
++  input C,
++  input CE, D, CLR
 +);
    parameter [0:0] INIT = 1'b0;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_D_INVERTED = 1'b0;
@@@ -265,11 -274,7 +286,13 @@@
    endcase endgenerate
  endmodule
  
 -module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 +module FDPE (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, PRE
++  (* clkbuf_sink *) 
++  input C,
++  input CE, D, PRE
 +);
    parameter [0:0] INIT = 1'b1;
    parameter [0:0] IS_C_INVERTED = 1'b0;
    parameter [0:0] IS_D_INVERTED = 1'b0;
@@@ -283,52 -288,38 +306,61 @@@
    endcase endgenerate
  endmodule
  
 -module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
 +module FDRE_1 (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, R
++  (* clkbuf_sink *)
++  input C,
++  input CE, D, R
 +);
    parameter [0:0] INIT = 1'b0;
    initial Q <= INIT;
    always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
  endmodule
  
 -module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
 +module FDSE_1 (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, S
++  (* clkbuf_sink *)
++  input C,
++  input CE, D, S
 +);
    parameter [0:0] INIT = 1'b1;
    initial Q <= INIT;
    always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
  endmodule
  
 -module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
 +module FDCE_1 (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, CLR
++  (* clkbuf_sink *)
++  input C,
++  input CE, D, CLR
 +);
    parameter [0:0] INIT = 1'b0;
    initial Q <= INIT;
    always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
  endmodule
  
 -module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
 +module FDPE_1 (
 +  (* abc_arrival=303 *)
 +  output reg Q,
-   input C, CE, D, PRE
++  (* clkbuf_sink *)
++  input C,
++  input CE, D, PRE
 +);
    parameter [0:0] INIT = 1'b1;
    initial Q <= INIT;
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
 -(* abc_box_id = 5 *)
  module RAM32X1D (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 +  (* abc_arrival=1153 *)
    output DPO, SPO,
 -  (* abc_scc_break *)
    input  D,
+   (* clkbuf_sink *)
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
@@@ -344,12 -335,14 +376,13 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 6 *)
  module RAM64X1D (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 +  (* abc_arrival=1153 *)
    output DPO, SPO,
 -  (* abc_scc_break *)
    input  D,
+   (* clkbuf_sink *)
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@@ -365,12 -358,14 +398,13 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 7 *)
  module RAM128X1D (
 -  output       DPO, SPO,
 -  (* abc_scc_break *)
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 +  (* abc_arrival=1153 *)
 +  output DPO, SPO,
    input        D,
+   (* clkbuf_sink *)
    input        WCLK,
 -  (* abc_scc_break *)
    input        WE,
    input  [6:0] A, DPRA
  );
@@@ -384,10 -379,33 +418,35 @@@
  endmodule
  
  module SRL16E (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 +  (* abc_arrival=1472 *)
    output Q,
-   input A0, A1, A2, A3, CE, CLK, D
+   input A0, A1, A2, A3, CE,
+   (* clkbuf_sink *)
+   input CLK,
+   input D
+ );
+   parameter [15:0] INIT = 16'h0000;
+   parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ 
+   reg [15:0] r = INIT;
+   assign Q = r[{A3,A2,A1,A0}];
+   generate
+     if (IS_CLK_INVERTED) begin
+       always @(negedge CLK) if (CE) r <= { r[14:0], D };
+     end
+     else
+       always @(posedge CLK) if (CE) r <= { r[14:0], D };
+   endgenerate
+ endmodule
+ 
+ module SRLC16E (
+   output Q,
+   output Q15,
+   input A0, A1, A2, A3, CE,
+   (* clkbuf_sink *)
+   input CLK,
+   input D
  );
    parameter [15:0] INIT = 16'h0000;
    parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@@ -404,13 -423,13 +464,16 @@@
  endmodule
  
  module SRLC32E (
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
 +  (* abc_arrival=1472 *)
    output Q,
 +  (* abc_arrival=1114 *)
    output Q31,
    input [4:0] A,
-   input CE, CLK, D
+   input CE,
+   (* clkbuf_sink *)
+   input CLK,
+   input D
  );
    parameter [31:0] INIT = 32'h00000000;
    parameter [0:0] IS_CLK_INVERTED = 1'b0;
diff --cc techlibs/xilinx/synth_xilinx.cc
index 8d0cf84f3,f058da83d..db8c9fa31
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -385,8 -423,10 +423,10 @@@ struct SynthXilinxPass : public ScriptP
  
  		if (check_label("map_luts")) {
  			run("opt_expr -mux_undef");
+ 			if (flatten_before_abc)
+ 				run("flatten");
  			if (help_mode)
 -				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
 +				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
  			else if (abc9) {
  				if (family != "xc7")
  					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
diff --cc techlibs/xilinx/xc7_brams_bb.v
index 56939089c,a43b4b5a1..5b40a457d
--- a/techlibs/xilinx/xc7_brams_bb.v
+++ b/techlibs/xilinx/xc7_brams_bb.v
@@@ -1,7 -1,7 +1,9 @@@
 +// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147
 +
  module RAMB18E1 (
+ 	(* clkbuf_sink *)
  	input CLKARDCLK,
+ 	(* clkbuf_sink *)
  	input CLKBWRCLK,
  	input ENARDEN,
  	input ENBWREN,