From: Jean-François Nguyen <jf@lambdaconcept.com>
Date: Tue, 16 Jun 2020 13:28:35 +0000 (+0200)
Subject: cxxrtl: restrict the debug info of a blackbox to its ports.
X-Git-Tag: working-ls180~468^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d98c3861dc702644e5cc333255726d1e1bf8e4f;p=yosys.git

cxxrtl: restrict the debug info of a blackbox to its ports.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 909e1325d..dada9ae64 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -1621,6 +1621,8 @@ struct CxxrtlWorker {
 			for (auto wire : module->wires()) {
 				if (wire->name[0] != '\\')
 					continue;
+				if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
+					continue;
 				count_public_wires++;
 				if (debug_const_wires.count(wire)) {
 					// Wire tied to a constant
@@ -1647,19 +1649,21 @@ struct CxxrtlWorker {
 					count_skipped_wires++;
 				}
 			}
-			for (auto &memory_it : module->memories) {
-				if (memory_it.first[0] != '\\')
-					continue;
-				f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
-				f << ", debug_item(" << mangle(memory_it.second) << ", ";
-				f << memory_it.second->start_offset << "));\n";
-			}
-			for (auto cell : module->cells()) {
-				if (is_internal_cell(cell->type))
-					continue;
-				const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
-				f << indent << mangle(cell) << access << "debug_info(items, ";
-				f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
+			if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
+				for (auto &memory_it : module->memories) {
+					if (memory_it.first[0] != '\\')
+						continue;
+					f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
+					f << ", debug_item(" << mangle(memory_it.second) << ", ";
+					f << memory_it.second->start_offset << "));\n";
+				}
+				for (auto cell : module->cells()) {
+					if (is_internal_cell(cell->type))
+						continue;
+					const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
+					f << indent << mangle(cell) << access << "debug_info(items, ";
+					f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
+				}
 			}
 		dec_indent();