From: Cole Poirier <colepoirier@gmail.com>
Date: Thu, 13 Aug 2020 19:05:10 +0000 (-0700)
Subject: dcache.py add initial imports
X-Git-Tag: semi_working_ecp5~367
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d992fe42e782b102eef2fd4c35a285abba32855;p=soc.git

dcache.py add initial imports
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 0eb44c06..71329987 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1,3 +1,19 @@
+"""Dcache
+
+based on Anton Blanchard microwatt dcache.vhdl
+
+"""
+
+from nmigen import Module, Signal, Elaboratable,
+                   Cat, Repl
+from nmigen.cli import main
+from nmigen.iocontrol import RecordObject
+
+from experiment.mem_types import LoadStore1ToDcacheType,
+                                 DcacheToLoadStore1Type,
+                                 MmuToDcacheType,
+                                 DacheToMmuType
+
 # --
 # -- Set associative dcache write-through
 # --