From: Florent Kermarrec Date: Tue, 24 Mar 2020 19:04:18 +0000 (+0100) Subject: boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. X-Git-Tag: 24jan2021_ls180~524 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8d999081e3b4f1d6f928b06f189a67a6ab985b5d;p=litex.git boards/targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support. --- diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index e3ca8683..edc020d7 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -22,7 +22,7 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # @@ -43,7 +43,7 @@ class _CRG(Module): p_CLK1_DIVIDE_BY = 1, p_CLK1_DUTY_CYCLE = 50, p_CLK1_MULTIPLY_BY = 1, - p_CLK1_PHASE_SHIFT = "-10000", + p_CLK1_PHASE_SHIFT = "5000", # 90° p_COMPENSATE_CLOCK = "CLK0", p_INCLK0_INPUT_FREQUENCY = 20000, p_OPERATION_MODE = "NORMAL", @@ -61,10 +61,7 @@ class _CRG(Module): self.cd_sys.clk.eq(pll_clk_out[0]), self.cd_sys_ps.clk.eq(pll_clk_out[1]), ] - self.specials += [ - AsyncResetSynchronizer(self.cd_sys, ~pll_locked), - AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked) - ] + self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked) # SDRAM clock self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk) diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 00d68793..2903a507 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -9,6 +9,7 @@ import argparse from fractions import Fraction from migen import * +from migen.genlib.io import DDROutput from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import minispartan6 @@ -26,27 +27,22 @@ from litedram.phy import GENSDRPHY class _CRG(Module): def __init__(self, platform, clk_freq): self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys_ps = ClockDomain() + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) # # # self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(platform.request("clk32"), 32e6) pll.create_clkout(self.cd_sys, clk_freq) - pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270) + pll.create_clkout(self.cd_sys_ps, clk_freq, phase=90) - self.specials += Instance("ODDR2", - p_DDR_ALIGNMENT="NONE", - p_INIT=0, p_SRTYPE="SYNC", - i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1, - i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk, - o_Q=platform.request("sdram_clock")) + # SDRAM clock + self.specials += DDROutput(0, 1, platform.request("sdram_clock"), ClockSignal("sys_ps")) # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(80e6), **kwargs): - assert sys_clk_freq == int(80e6) platform = minispartan6.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -57,7 +53,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cmd_latency=2) self.add_sdram("sdram", phy = self.sdrphy, module = AS4C16M16(sys_clk_freq, "1:1"), diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index 17b30a52..98a5f30a 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -40,8 +40,8 @@ class _CRG(Module): self.submodules.pll = pll = ECP5PLL() self.comb += pll.reset.eq(rst) pll.register_clkin(clk25, 25e6) - pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11) - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) # SDRAM clock @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) self.add_sdram("sdram", phy = self.sdrphy, module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1"),