From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Nov 2013 19:29:07 +0000 (+0100)
Subject: Added module->avail_parameters (for advanced techmap features)
X-Git-Tag: yosys-0.2.0~306
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8dafecd34d772b1d9ec190b39913b236cdc8fb17;p=yosys.git

Added module->avail_parameters (for advanced techmap features)
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 66b670c7a..f7e7b852c 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -805,7 +805,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_TASK:
 	case AST_FUNCTION:
 	case AST_AUTOWIRE:
-	case AST_PARAMETER:
 	case AST_LOCALPARAM:
 	case AST_DEFPARAM:
 	case AST_GENVAR:
@@ -814,6 +813,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_GENIF:
 		break;
 
+	// remember the parameter, needed for example in techmap
+	case AST_PARAMETER:
+		current_module->avail_parameters.insert(str);
+		break;
+
 	// create an RTLIL::Wire for an AST_WIRE node
 	case AST_WIRE: {
 			if (current_module->wires.count(str) != 0)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4b790cbde..5873c3694 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -257,6 +257,7 @@ struct RTLIL::Design {
 
 struct RTLIL::Module {
 	RTLIL::IdString name;
+	std::set<RTLIL::IdString> avail_parameters;
 	std::map<RTLIL::IdString, RTLIL::Wire*> wires;
 	std::map<RTLIL::IdString, RTLIL::Memory*> memories;
 	std::map<RTLIL::IdString, RTLIL::Cell*> cells;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 0bef2b62f..bd3d223b6 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -223,7 +223,7 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
 						continue;
 					if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
 						continue;
-					if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0)
+					if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
 						goto next_tpl;
 					parameters[conn.first] = conn.second.as_const();
 				}
@@ -232,6 +232,9 @@ static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::
 		next_tpl:
 					continue;
 				}
+
+				if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
+					parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
 			}
 
 			std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
@@ -475,7 +478,10 @@ struct TechmapPass : public Pass {
 		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
 		for (auto &it : map->modules) {
 			if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").str.empty()) {
-				celltypeMap[RTLIL::escape_id(it.second->attributes.at("\\techmap_celltype").str)].insert(it.first);
+				char *p = strdup(it.second->attributes.at("\\techmap_celltype").str.c_str());
+				for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
+					celltypeMap[RTLIL::escape_id(q)].insert(it.first);
+				free(p);
 			} else
 				celltypeMap[it.first].insert(it.first);
 		}